Hardware

Scan Vector Compression/Decompression Using Statistical Coding

Statistical Analysis / Data Compression / VLSI / Data Engineering / Hardware / Decoding / Test Data / Chip / Boolean Satisfiability / Digital System Testing / Channel Capacity / Test Data Compression / Decoding / Test Data / Chip / Boolean Satisfiability / Digital System Testing / Channel Capacity / Test Data Compression

Special-purpose computer for holography HORN2

Holography / Mathematical Sciences / Hardware / Physical sciences / High Speed / Hologram / Light Intensity / Floating Point / Hologram / Light Intensity / Floating Point

Apostila de Arduino - Alvaro Justen

Arduino / Eletrônica / Hardware / Software Livre / DIY

A comparative study of encodings to design combinational logic circuits using particle swarm optimization

Computer Science / Computational Modeling / Evolutionary Computation / Genetic Algorithms / Integer Programming / Convergence / Comparative Study / Stability / Particle Swarm Optimization / Proceedings / Hardware / Acceleration / Robustness / Circuit Design / Encoding / Design optimization / Evolvable Hardware / Logic Design / Performance Indicator / Particle Swarm Optimizer / Logic circuits / Combinational Circuits / Convergence / Comparative Study / Stability / Particle Swarm Optimization / Proceedings / Hardware / Acceleration / Robustness / Circuit Design / Encoding / Design optimization / Evolvable Hardware / Logic Design / Performance Indicator / Particle Swarm Optimizer / Logic circuits / Combinational Circuits

Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

A formal approach to system level design: metamodels and unified design environments

Computer Architecture / Computational Modeling / Systems Analysis / Hardware/Software Co-Design / Formal Semantics / Space Exploration / Hardware / Formal Specification / Process Design / Design Methodology / Logic Language / System-level design / Logic Design / Platform Based Design / Space Exploration / Hardware / Formal Specification / Process Design / Design Methodology / Logic Language / System-level design / Logic Design / Platform Based Design

Mitra Distributor Kyoritsu Indonesia

Hardware

A lossless compression method for internet packet headers

Computer Architecture / Data Compression / Hardware / Availability / Bandwidth / Transport Protocols / Internet / Tcpip / Lossless Compression / Compression Ratio / Transport Protocols / Internet / Tcpip / Lossless Compression / Compression Ratio

An environment for dynamic component composition for efficient co-design

Intellectual Property / System Engineering / Hardware / Computer Languages / Scripting Language / DATE / Automatic code generation / Embedded Computing / Simulation Models / Simulation Model / Component composition / DATE / Automatic code generation / Embedded Computing / Simulation Models / Simulation Model / Component composition

A multiprocessor self-reconfigurable JPEG2000 encoder

Computer Architecture / Field-Programmable Gate Arrays / Processor Architecture / Hardware / Field Programmable Gate Array / JPEG / IPDPS / Multi-threading / Embedded System / Dynamic Reconfiguration / JPEG / IPDPS / Multi-threading / Embedded System / Dynamic Reconfiguration

MAC-SCC: a medium access control protocol with separate control channel for reconfigurable multi-hop wireless networks

Distributed Computing / Optimal Control / Wireless networks / Probability / Simulation / Performance Evaluation / Mobile Ad Hoc Network / Hardware / Bandwidth Allocation / Ad hoc network / Spread Spectrum Communication / Medium Access Control / Wireless Application Protocol / Statistical Model / Bandwidth / Network Simulator / MAC Protocol / Electrical And Electronic Engineering / Data Transmission / Performance Evaluation / Mobile Ad Hoc Network / Hardware / Bandwidth Allocation / Ad hoc network / Spread Spectrum Communication / Medium Access Control / Wireless Application Protocol / Statistical Model / Bandwidth / Network Simulator / MAC Protocol / Electrical And Electronic Engineering / Data Transmission

Proyecto de Educación a Distancia

EAD / Hardware / TICs aplicadas a la Educacion

Energy efficiency in large-scale distributed computing systems

Energy efficiency / Clusters / Computers / Distributed Processing / Hardware / Energy Efficiency

Electronic data interchange using two dimensional bar code

Documentation / Hardware / Robustness / Prototypes / Data Handling / Electronic Data Interchange

Energy efficiency in large-scale distributed computing systems

Energy efficiency / Clusters / Computers / Distributed Processing / Hardware / Energy Efficiency

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