X-Band to W-Band Frequency Multiplier in 65 nm CMOS Process

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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 8, AUGUST 2012

X-Band to W-Band Frequency Multiplier in 65 nm CMOS Process Nadav Mazor and Eran Socher, Senior Member, IEEE

Abstract—A compact single chip x9 frequency multiplier from X band to W band implemented in 65 nm CMOS is presented. A chain of five transformer coupled stages is used, including two triplers, realized with differential common source amplifiers at class-C mode. The circuit reaches saturated output power of 3 2 dBm at 91.8 GHz with a 7.2% bandwidth from 88.9 to 95.5 GHz. The suppression of unwanted harmonics is better than 16 dBc across the bandwidth. The core design occupies 246 m 706 m and consumes 120 mW from a 1.2 V supply. Supply voltage increase to 1.3 V yields a peak output power of 2 7 dBm and 160 mW of dc power. Index Terms—CMOS millimeter-wave frequency multiplier, transformers, W-band, X-band. Fig. 1. Circuit schematic view.

I. INTRODUCTION HE frequency window around 94 GHz is interesting for various wireless applications due to the relatively low atmospheric attenuation. These applications include RADAR and imaging, on one hand, and Gigabits per second (Gbps) wireless links on the other. If coherent detection of signal is desired, a frequency and phase locked local oscillator (LO) is needed at that frequency range. At lower frequencies, most systems use a synthesizer to implement the LO, based on a phased locked loop (PLL) with a voltage controlled oscillator (VCO) that operates at the LO frequency and a low frequency external reference. At W-band, LO synthesis is not trivial. If a W-band VCO is used [1], tuning range is limited and has trade-offs with the phase noise and the output power. Moreover, power and area are also consumed in the long divider chain that is needed. Recently, CMOS W-band synthesis was proposed using frequency multiplication using injection-locked frequency triplers [2]. This allows easier implementation of the synthesizer at lower frequency, with better fractional locking range. Although this approach is useful in extending the output frequency range, the output power drops as the frequency difference from the freerunning increases. Moreover, if multiple W-band LO signals are needed, e.g., in a multiple element antenna array, multiple Ka-band PLLs would be required, consuming power and area. In this work, we propose the use of a x9 active multiplier as a mean to generate a W-band mW-level LO signal out of an X-band reference. X-band signals could be distributed with much lower loss and dispersion compared to Ka-band signals,

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and the X-band reference signal could be more easily generated with lower phase noise, wider bandwidth and more output power. Multiplying by 9 would simply add 19 dB to the phase noise, while the higher available input power makes harmonic generation easier in the multiplier chain. In Section II the circuit and layout design are described; Section III presents the measurement results and Section IV concludes the work and compares it with the state-of-the-art. II. CIRCUIT DESIGN A. Topology The circuit, shown schematically in Fig. 1, was designed as a chain of differential Common Source (CS) NMOS amplifiers. The two multipliers are biased at class-C, generating a third harmonic differential signal, while suppressing the even harmonics. The input is matched at the input frequency and the output is matched at the output third harmonic frequency. The three amplifier stages are placed before, in-between and after the active multipliers. The amplifiers are biased at class-A. Transformers are used throughout the design for matching, and provide also the transistor biasing through the center tap points of the symmetrical coils of the transformers, [3]. This form of interstage matching has the advantages of compact area, low insertion loss and providing a virtual RF ground along the symmetry axis. The input and output transformers also serve as baluns, interfacing between the input and output single ended signals and the balanced signal flowing through the differential circuit. B. Schematics

Manuscript received January 24, 2012; revised May 01, 2012; accepted June 27, 2012. Date of publication July 13, 2012; date of current version August 03, 2012. The authors are with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2012.2207708

With a 1.2 V power supply, NMOS low power regular threshold voltage transistors were used, all with minimum channel length of 60 nm. All transistors are 32 fingers of width each, except for the output W-band stage that uses 2 1 finger width to achieve better Gmax by lowering the gate resistance which is more detrimental at high frequencies.

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MAZOR AND SOCHER: X-BAND TO W-BAND FREQUENCY MULTIPLIER IN 65 NM CMOS PROCESS

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Fig. 4. Measured versus simulated output power as a function of output frequency. Fig. 2. 3-D views of transformers, TR1 (a) TR2 (b) TR3 (c). TABLE I SUMMARY OF TRANSFORMERS PERFORMANCE

Fig. 5. Measured output power and conversion loss at 93.6 GHz versus input power.

m2 706 m).

Fig. 3. Die micrograph of the circuit (core area 246 

The amplifying stages are biased with 0.9 V at the gate, while a gate bias of 0 V is used in the class-C multiplier stages. Class-C operation was preferred to clipping for third harmonic generation due to its better efficiency and harmonic rejection. C. Transformers The interstage transformers were mostly designed with the goal of simultaneous conjugate matching, as described in [4], with the input and output stages matched to external 50 terminations. The two transformers at the inputs of each multiplier stage were designed with the objective of maximizing the voltage swing at the gates of the multiplier, in order to maximize the generation of current at the third harmonic due to transistor non-linearity. Each transformer was simulated and optimized using electro-magnetic simulation MOMENTUM™ which generated an -parameters block for each transformer. Fig. 2 depicts 3-D views of the last three transformers used in the design.

Stacking of two coupled inductors was used to maximize coupling and minimize the insertion loss at mm-wave frequencies. -thick The primary coil was implemented in the top 3.25 copper metal, while the secondary used the 0.5 -thick copper metal just below it. Table I summarizes the simulated performance of the transformers used in the design. III. EXPERIMENTAL RESULTS The fabricated circuit, shown in Fig. 3, was characterized using on-chip probing, an Agilent signal generator (PSG) was used to sweep an input frequency range of 9 GHz to 11 GHz. A 75–110 GHz harmonic mixer was connected to the output, together with a 50 GHz spectrum analyzer (PSA) to inspect the output spectrum at both the expected output frequency range of 81–99 GHz and the other spurious harmonics of the input signal. The results shown in Figs. 4–6 take into account the setup losses and were also calibrated using a diode-based power detector. Fig. 4 shows the measured frequency response of the multiplier with an input power of 20 dBm. At 1.2 V dc supply and an average 120 mW of dc consumption was measured, resulting in a bandwidth of 6.6 GHz between 88.9 GHz and 95.5 GHz. The center frequency measured was 91.8 GHz output power and while working with with 1.3 V dc supply (160 mW). Fig. 5 illustrates the output power response and conversion loss at 93.6 GHz.

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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 8, AUGUST 2012

TABLE II COMPARISON WITH STATE OF THE ART W-BAND MULTIPLIERS

Fig. 6. Measured output power versus output frequency for different input power levels [dBm].

Fig. 7. Measured rejection of input harmonics at the output versus input frequency.

When the input power is lower than 8 dBm, the output power is lower than due to the third harmonic generation dependence upon signal swing. A peak conversion loss of 16 dB is reached for an input power of 10 dBm. Further increase of the input power does not increase the peak output power significantly, but provides an increase in the bandwidth by saturating the output power levels of neighboring frequencies, as shown in Fig. 6. The chosen input power level should therefore be a tradeoff between conversion loss and bandwidth requirements. In Fig. 7 a summary of harmonic spurious rejection is shown for the different harmonics of the input frequencies across the bandwidth while input power is at maximum of 20 dBm. The output spectrum shows rejection of more than 15.7 dBc of all harmonics. Rejection of the third harmonic is better than 51 dBc and rejection of the input is better than 30 dBc. The phase noise of the X-band source and the W-band output and , rewere also measured as spectively, at 10 kHz offsets, corroborating the ideal 19 dB contribution of x9 multiplication. IV. CONCLUSION A single chip W-band x9 multiplier has been realized in a standard 65 nm CMOS process consuming an area of only

, by employing interstage transformer coupling, and 0.31 dc power of 120 mW from a 1.2 V supply. The circuit achieved . a 6.6 GHz bandwidth and a peak output power of A comparison is shown with state-of-the-art W-band frequency synthesis in Table II. While HEMT-based multipliers [5], [6] are still hard to compete with in terms of bandwidth and output power levels, this CMOS-based work has an advantage in terms of power consumption and chip area. The CMOS implementation in [2], using a Ka PLL and ILFT, consumes even less dc power with comparable bandwidth and area, but achieves at least 10 dB less in output power. The input stage of the design proved to be limiting the input power into the first tripler stage and had to be driven well into potentially harmful compression. The design could thus be simply improved by removing the input X-band stage. Further improvements such as inter stage harmonic rejection can lead to further improvements in both the output power and the bandwidth.

REFERENCES [1] E. Socher and S. Jameson, “Wide tuning range W-band Colpitts VCO in 90 nm CMOS,” Electron. Lett., vol. 47, no. 22, pp. 1227–1229, Oct. 2011. [2] Z. Chen and P. Heydari, “An 85–95.2 GHz transformer-based injection-locked frequency tripler in 65 nm CMOS,” in IEEE MTT-S Int. Dig., 2010, pp. 776–779. [3] Z. Jian, B. Mingquan, D. Kuylenstierna, L. Szhau, and H. Zirath, “Broadband Gm-boosted differential HBT doublers with transformer balun,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 11, pp. 2953–2960, Nov. 2011. [4] A. Vishnipolsky and E. Socher, “A compact power efficient transformer coupled differential W-band CMOS amplifier,” in Proc. IEEE 26-th Conv. Elect. Electron. Eng. Israel, Eilat, Israel, 2010, pp. 869–872. [5] I. Kallfass, H. Massler, A. Tessmann, A. Leuther, M. Schlechtweg, and G. Weimann, “A broadband frequency sixtupler MIMIC for the W-band with 7 dBm output power and 6 dB conversion gain,” in IEEE MTT-S Int. Dig., Jun. 2007, pp. 2169–2172. [6] R. Weber, U. Lewark, A. Leuther, and I. Kallfass, “A W-band 12 multiplier MMIC with excellent spurious suppression,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 4, pp. 212–214, Apr. 2011.

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