Two-dimensional optical interconnect between CMOS IC\'s

Two-Dimensional Optical Interconnect between CMOS IC’s L. Vanwassenhove(l), R. Baets( I), M. Brunfaut(2), J. Van Campenhout(2), J. Ha11(3), K. Ebeling(4), H. Melchior(5), A. Neyer(6), H. Thienpont(7), R. Vounckx(8), J. Van Koetsem(9), P. Hercmans(lO), F.-T. Lentes(1 I), D. Litaize(l2) (1)Ghent University - IMEC, Department of Information Technology (INTEC), Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium phone ++32 9 264 33 16, fax ++32 9 264 35 93, e-mail l u c . v n n ~ \ ~ ; r r s e n l i ~ ~ ~ ~ ~ ( ~ i ~ i n t c c . i - i i ~ . i i c . l ~ c (2) Ghent University - IMEC-ELIS, Belgium, (3) Marconi Caswell Limited (MCL), U.K., (4) University of Ulm, Dept. of Optoelectronics, Germany, (5) Eidgenossische Technische Hochschule Ziirich, Mikro- und Optoelektronik , Switzerland, (6) University of Dortmund, FB Elektrotechnik, Mikrostrukturtechnik, Germany, (7) Vrije Universiteit Brussel, Lab for Photonics, Belgium, (8) Vrije Univcrsiteit Brussel, Electronics Department, Belgium (9) Framatome Connectors International. Belgium, (10) IMEC - MAP, Belgium, (1 1) Schott Glass, Germany, (12) Institut de Recherche en Informatique de Toulouse (IRIT), Francc Abstract The main reason for the expected I/O-bottleneck in future data processing systems, is the increase in CMOS ICcomplexity, in terms of chip size, number of 110 pads and clock frequency. It is generally perceived that the number and the difficulty of the technical challenges continue to increase as technology moves forward, as pointed out io the 1999 SIA Roadmap. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion, EMI) result in an increasing mismatch between silicon processing capabilities and interconnect performance, pushing packaging costs and required effort to significantly higher levels. Due to the envisaged importance for IC development well within the next decade, optoelectronic interconnects have been chosen as a subject of focused proactive research, an initiative called “Advanced reseach initiative in microelectronics: optoelectronic intercoonects for integrated circuits”, (MEL-ARI-OPT0 Cluster’). In the framework of this initiative, Optical I/O over the entire chip area is pursued as a possible solution to these interconnection problems in the project OIIC2 (“Optically Interconnected Integrated Circuits”). The central issue of OIIC concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers highthroughput data interconnects on inter-chip and Multi-Chip Module (MCM) level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-ofthe-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 pm pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, componcnts, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-dimensional architecture, conceptually consisting of a number of electronic planes (electrical FPGAs), that are interconnected

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bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8 x 8 array of simple configurahle logic blocks (a 4-bit function table. one flipflop), interconnected by a programmable 6 x 6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8x8 source arrays (either LEDs or VCSELs) and two 8 x 8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbitis, a typical data rate for highend commercial FPGAs. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8 x 16 Plastic Optical Fiber (POF) ribbons. The two outer chips are equipped with 2 x (8 x 8) ribbons with horizontal insertion POF-ribbon connectors allowing a closed, toroidal interconnect, or an open optical I/O access to the system. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive aligument of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements will he discussed.

The System Demonstrator

1.Introduction It is our goal to demonstrate the viability of massively parallel optical interconnects between electronic VLSI chips. The demonstrator will be connecting three packaged, programmable chips, through area optical interconnect (256 optical links per chip). These chips harbour a programmable FPGA-architecture, On the chip, digital and analogue Functiooality (separate drivers and receivers for each individual optoelectronic component, and the FPGA functionality) are intermixed. For the CMOS, an external 2000 Electronic Components and Technology Conference

foundry scrvice delivering 0.6 pin technology is used. Aggregate bit rate (U0 pcr chip) will excced I O Gbis. This is done through the dcvelopnient of the technology necessary for the realisation of such interconueclions, and the definition and realisation of a systems architecture in which these interconnections play a meaningful role. In this section, the design and fabrication of a system dcmonstrator will be discussed.

The optoelectronic FPGA dcmonstrator is at the time of writing, in the final stage of realisation. This involves besides the actual CMOS FPGA, the design and implemeutation of various light sources and detectors, as well as the analogue CMOS interface circuits; the building blocks of the optical pathways, which are based upon plastic optical fibre; and the methodology for hybrid assembly, packaging and passive alignment of all components. 2. The CMOS circuit functionality

l’igure la, b: l h e system demonstrator consists of 3 PGA packages, each holding a CMOS FPGA-chip with analogue drivers and receivers. 00top of the CMOS, arrays of optoelectronic Components are hybridised. The chips arc optically interconnected by arrays of plastic optical fibre, in ribbons of 128 channels. Not shown on the graph is the closing optical loop with a newly developed 8x8 optical connector for the channels. Followiug characteristics are envisioned: function : intorconnect betwccn 3 packagcd FPGA chips wavelength : 980 nm, pitch of thc optical components: 250 pm sources : MCLED vcrsion (two 8*8 arraydchip) and VCSEL version (two 4% arrays/chip) detectors : hybrid InGaAdlnP detectors analogue circuits : optimized drivers and receivers digital function : FPGA-bascd architecture clock speed : 150 Mb/s per channel aggregate bitrate : > 10 Gb/s aggregate bitrate per chip conuectorisation : horizontal insertion 8x8 POF-ribbon connector mounting : flip-chip mounting of OE-compouents directly on CMOS Morc on the concepts and choices made earlier on in the project can bo found in dhocdt et al.’

Multi-FPGA systems have been identified as good candidates for the introduction of low level optoelectronic interconnects, from both the systems and the purely demonstrator related points of view ‘. FPGAs are electronic components that can be programmed to implement arbitrary electronic designs. As programming can be done in-situ and repetitively, FPGAs are being applied in quickly growing numbers in a large variety of applications’. They are currently being used as rcplacenients for random logic in situations where ASIC design is not indicated; as configurable processors and coprocessors; and as fast prototyping platforms for real-time or uear real-time prototyping of VLSI designs before actual chip fabrication. In these last two applications, iuvariably multi-FPGA systems are required. Unfortunately, their flcxibility (programmability) comes with a price. For a given silicon area, the sizes of designs that FPGAs can harbour are much smaller then ASIC implementations and to make things worse, FPGAs are frequently plagued by a lack of interconnect capabilities6. Multi-FPGA systems in particular suffer from the lack of inter-chip interconnect capability. Optoelectronic a r e a 4 0 for multi-FPGA systems would offer a definite advantage in terms of interconnect capability’, as the speed of the (programmable) electrical on-chip or off-chip interconnect system is lower than that of dedicated ASICs. As a result, optical interconnects, even if they are not optimised for latency, provide a viable substitute and extension of the electrical interconnect system in multi-FPGA systems’. In demonstrator terms, FPGAs have the following advantages: only one type of silicon chip has to be designed and produced. Virtually the entire chip can be tested electrically before the hybridisation with the optical components takes place. FPGAs have a regular internal structure that blends well with the ultimate goal of regularly spaced and interlaced optical components across the surface of a silicon chip. FPGAs contain a lot of redundancy due to their programmability and regularity. This provides a welcomed robustness against local defects in the prototype demonstrator. No prior limits are imposed onto the actual demonstrator functionality. FPGAs allow a meaningful demonstration of logic-level optical interconnect, which is desirable for its relative simplicity, but which does not seem to be a sensible approach outside the context of programmable logic. The CMOS FPGA chips are small, custom made 8 x 8 FPGAs, with an optically augmented interconnect fabric. Per configurdble logic block, there are two bidirectional links. interconnecting to the corresponding points in the 232

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Figure 3: single transmitter cell

neighboring elcctrical layers. Conceptually, these layers are located beneath and over the current layer, respectively. The physical realisation of the optical pathway will allow the unfolding of thc system into a conventional planar one, without however having to implement the high-density interconnect in the support substrate.

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Figure 4: single receiver cell Driver and receiver cells are designed with as boundary conditions the requircd 160MbiWs performance, minimal power consumption, opto-component specifications and available chip area. Measurements show, that the electronic driver works fine. As expected a line bitrate up to several 100 MbiWs can be measured. The power consumption of single driver ccll, measured with a commercially available VCSEL, at 160 MbiWs operation speed, 3.3 V power supply, 2.8mA bias and 2mA modulation current is 19mW. Mismatch in series resistance hetwcen this emitter and the components actually used in the project is accounted for. Receivers have also shown to fulfill the specifications. Although higher speeds are feasible with the given designs, it can assumed however that the performance of the actual built will be limited by the CMOS fabrication process used and the interconnections to the IiO pads.

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Efforts are concentrated on both LED’s and VCSEL’s. Because both components offer rather different categories of advantages, it is still unclear, which of the two device types are to he preferred in this particular application area (dhoedt et ai3). 3.a. VCSEL’s Two-dimensional VCSEL arrays of 4 by 8 components on a 250 pm pitch were fahricated, emitting at 980 nm (emitting trough the device substrate). Figure 5 shows optical and electrical characteristics of a bottom cmitting selectively oxidised 4 x 8 VCSEL array as a function of lascr driving current. The active diameter of an individual laser is about 7 pm. The dissipated electrical powcr per channel at the target optical output powcr of 1 mW is 2.8 mW and the voltage drop across the laser is only 1.8 V at this operation point. Threshold current and threshold voltage of the transverse multimode lasers are 0.8 mA and 1.5 V, respectively. The I-V characteristics are quite homogeneous across the sample. At

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an average optical output power of 0.5 niW the analogue modulation bandwidth of the lasers is 4.7 GHz, as shown in figure 6 . Bandwidths exceeding 10 GHz have been measured at higher bias currents.

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Frequency (GHz) Figure 6 : Small-signal modulation response of a 7 pm VCSEL biased at an optical output power of 0.5 mW 3.b.MCLED's Although highly efficient microcavity LED's can be fabricated (external efficiencies up to 22.X % reported9) , the requirement for efficient coupling to a limited (although relatively high) numerical aperture medium implies a reduction of the device efficiency: extremely high extraction valucs are in this device type relatively tightly related to a broad angular emission. Therefore, devices have been optimised for efficient coupling to plastic optical fibre, rather than for shear extraction efficiency'". Device layout and cross section are similar to the case of the VCSEL's to ensure mounting compatibility. Power and voltage versus current characteristics are shown in figure 7 for a 50 pm device. At 5 mA drive current, the series resistance of this device is as low as 2OCL To measure the speed characteristics of the MCLED' s, arrays were flip-chip mounted onto a high-speed carricr. The rise time was measured using a high-speed voltage pulse generator. Open eye-diagrams at bit ratcs over 500 Mbit/s are realisable, using small MCLED' s (40 pm mesas) driven at high current levels, as shown in figure 8. Measurements at speeds up to lGbitis have also been carried out.

Figure 8: eye-diagram of 40 pm mesa MCLED, driven by 3V PRES-signal, coupled to multimode glass fibre. Bitrate shown is SOOMbit/s

4. Optical Pathways One has to realise that the choice of an optical pathway has a profound impact on the way a system is assembled at the board (or MCM) level. The best choice will not only be a function of optical performance but also of reliability, ruggedness, practicality and obviously cost. Within the project three options for the optical pathway are being studied: 2D arrays of POF, a free space approach based on micro-optics (lenses, mirrors) in PMMA, and an image fibre bundle approach. The FPCA-based system demonstrator built in the project is based on the POF-array system. 4.a. POF-array pathway Inter-MCM interconnect requires a flexible transmission medium, preferably with possibilities for connectorisation. The flexibility of the interconnect medium, in combination with low bending radii required (due to headroom limitations) and the parallel nature of the interconnect favor the use of a fairly new product: small diameter plastic optical fibre". Relative ease of termination together with the advantages already mentioned is considered highly favorable, but on the other hand, long-term reliability of the material could presumably pose problems in very demanding applications. Optical pathways have been fabricated using Toray's PGR-

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FBI25 fibre. The numerical aperture of this fibre is high (typically 0.5), facilitating strong bending without excessive loss, and the diameter can be as small as 125 pm (120 pm core). Main drawback of this medium of the rather high absorption (about 12 dBlm at 980 nm, about 6 dBlm at 850 nm). For bend radii larger than 2 mm excess losses do not exceed 0.5 dBl90". Basic part of the OPB (Figure 9) is the socalled OPB hole plate in which the POFs are aligned. These 500 pm thick PMMA plates are microstructured by high precision drilling and milling. The plate shown in figure 9 is used for the system demonstrator.

Figure 9: SEM photo of a bole plate with 5 2 x8 arrays of 130 pm-holes and 2 699 pm steel guide pins for the alignment to the opto-electronic component

build-up is shown in Figure 11. A multi-channel free-space optical bridge was designed and fabricated as technology demonstrator, shown in Figure 12, to interconnect two 2x8 VCSEL and detector arrays flip-chip mounted a n the CMOS chip. Here the micro-lens arrays, positioned above the emitters, collimate the different beams, while the second micro-lens array refocuses the beams onto the detectors. The single mode input fiber with a NA=O.11 was used to mimic the emission characteristics of a VCSEL source whereas a multi-mode fiber with a NA=0.2 and a core diameter of 50 vm simulated the photo-detector. The distance traveled within the bridge is 8 mm and corresponds to an on-chip interconnection distance of I .6 mm. The optical transfer efficiencies for the 16 channels were measured to be in the range of 40% to 46% with a cross-talk between neighboring channels of -22dB to -27dB. To demonstrate the potentialities for high bandwidth intra-MCM data communication the single mode input fiber was connected to a standard telecommunication card operating at 1300 nm on the OC-12 SONET carrier level, generating a quasi-random 622Mbls bit stream.

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Fig.1 1: Schematic drawing of the frec-space module aligned with the CMOS chip.

Figure IO: Cross-section of the Optical Pathway Block

A first implementation of this concept realised a 2x8 optical link with individual POF's. For an interconnect distance of 50 cm, a total optical loss of 8.5 dB was found at h=980 nm, while optical cross talk was below -35dB. In view of the anticipated need for connectorisation, connectors for 2x8 POF arrays and 8x8 POF arrays (pitched at 250 vm in thc two dimensions) have been developed. The connectors will be deployed to optically interconnect the outcr 2 FPGA chips. The optical pathways for connecting the different FPGA chips have been fabricated. They consist of two arrays of 8x8 POF ribbons.

4.b. Intra-MCM interconnect Besides flexible inter-MCM interconnection modules we have fabricated scalable, rigid optical pathway blocks with the potential for Tbls.cn? aggregate bit rate capacity over intraMCM interconnection distances. Based on a confocal optical design this free-space demonstrator component was fabricated in PMMA using deep proton lithography. The schematic

Fig.12: Photo of the free-space plastic optical pathway block (a), detail of the lenslet arrays on the substrate bottom (b), close-up of the 200 micron diameter lenslets (c). 235

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5. Hybrid photodetectors In view of the rather broad radiation pattern and the diameter of the POF, rather large photodetectors are required. The diameter of the deviccs, 150 pin, is obtained by optimising a combined efficiency - cross talk criterion, and results i n a depletion capacitance of 1.4 pfi. As can be seen from figure 13, special carc has been taken to avoid cross talk by etching recesses and light blocking areas. I ht-blocking coating &tionai) \

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The experimental characteristics include dark currents below 50 nA at 5 V reverse bias, responsivities of 0.69 A/W for 980 nm illumination, optical crosstalk between nearest neighbour photodiodes of -32 dB. 2. Opto-SiCMOS assoiiibly on cnnicr tile

6. Packaging approach Within the limits of the ineasnrcment techniques, there is essentially no difference in the performance of the detector or VCSEL chips after mounting, compared to the probed values observed before solder reflow. In figure 14, 2 detector arrays are mounted in the upper right corner and lower left corner. The other 2 chips are VCSEL arrays. A schematic view of the finalised OIIC demonstrator module, using the POF approach, is given in figure 15. The key problem in this arrangement is that alignment belwecn POF-array and the opto-electronic device arrays is jeopardised by a cascade of alignment steps: ( I ) mask level alignment errors between active area and solder bumps, (2) solder bump misalignment, (3) solder bump positioning error on the CMOS, (4) CMOS chip positioning error, (5) carrier guide pin-hole alignment, ( 6 ) guide-pin alignment tolerance, (7) hole positioning error in the pathway block, (8) positioning error of the POF’s in the optical pathway block. A passive alignment schcme would result in excessive misalignment levels, in hlrn implying a severe optical power penalty and intolerable cross talk levels. Therefore, a special alignment process has been devised, allowing to reduce lateral and height misalignment to about 20 pm. This approach is based on index alignment of a spacer through the use of a master pick-up tool. More on the mounting and packaging can bc found in Hall et al.”

Figure 15: Schematic view of assembled inter-MCM optical interconnect demonstrator

Figure 16: Wirebonded system demonstrator chip, for testing of the FPGA functionality. No optocomponents have been hybridised on this chip 236

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The hybridisation showed 100% mounting yield. Somc flaws in the chip design could be detected, but the robust FPGA design cnables the circumventioii of these artifacts. First single clianncl links could be set up. The demonstrator will enable experiments aimcd at extraction of concrete data like power consumption, relative space requirements, achicvable delay and power dissipation. Acknowledgments This work has been partly fundcd by the European Commission, through the ESPRIT-MELARI project 22641 (OIIC) and by the Swiss Federal Office for Bducation and Science (Bcrnc). The authors from Ghent University also acknowledge the fnnding by the Inter University Attraction Poles Program IUAP. References Figure 17: Final assembly, with the optical pathway aligned and monntcd on top of the CMOS. Link Experiments In the first phase of the project test chip designs were submittcd to the foundry. These were designed to establish intra chip link tests, or intcr chip tests between sevcral chips. Limited digital hardware was included together with control circuitry for the testing of the optical channels. These chips had only 2x8 rows of driver and receiver circuitry respectively. Measurements were carried out examining required output power for a VCSEL array or an LED array. The output power was between 14 and 22 pW per mi\ modulation current, using a POF fibre of 10 cin long, optimally aligned above the surface of the source chip. With the VCSEL unit in the same setup and a bias current of 0.9 mA, between 80 and 160 pW increment on the output power per niA modulation current was measured. Supply voltage of the chips was 2.W. Tum on and turn off jittcr of the sources were measured. The results showed that the jitter on the source sidc of the system was very low with respect to the total jitter measured on a complete link, and several reasons for this were identified, among which receiver behaviour, available amount of light etc. Initial tests on a partially populated system demonstrator chip (using ai1 LED array as sources) show 100% yield on transmittcr and detector array flip-chip moimting, and correct functioning of' driver and receiver functionality, and manchester encoding and decoding hardware. FPGA functionality could be tested earlier and proved to be working properly. The supply voltage of the chip is 3.3V, and 2.5mA modulation current for an LED yields a functional link through a 20 cm long POF fibre. When the modulation current for all the LED's (32 in this case) goes up to 6 mA, current drawn is less then 1.2A. Conclusions The CMOS chip design and fabrication, with the analog driverireceiver arrays and thc digital logic is finished and alrcady partly tested. In figurc 16, a wirebonded system demonstrator is shown. At the time of writing, first hybridisation steps of opto-chips on thcse chips arc initiated.

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'http://www.cordis.lu/esprit/src/mclari.htm B. Dhoedt, et al.: "Optically interconnected integrated

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circuits to solve tbc CMOS interconnect bottleneck", procecdings of the 48"' ECTC conferencc Vol. Nr. 25-28 May 1998, Seattle, Washington, USA, pp, 992-998 J. Van Campenhout, et al, "Optoelcctronic FPGA's", IEEE journal of selected topics in quantum clectronics MarchiApril 1999, Volumc 05, Number 02 J. Cong, and C. Ebcliiig, guest editors. Special Section on Field Programmable Gate Arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(2), June 1998 S. Haiick. The Roles of FPGAs in Reprogrammable Systems, Proceedings ofthe fEEE, 86(4):615-638, April 1998 J. Depreitcrc, H. Van Marck, and J. Van Campenhout, A quantitative analysis of the benefits of the use of a r e a 4 0 pads in FPGAs, Microprocessor.v and Microsystems, 21(2):89-97, October 1997. J. M. Van Campenhout, Optics and thc CMOS interconnection problem: a systems and circuits perspcctive, International Journal of' Optoelectrunics, 12(4):145-154, 1998

' H. De Ncvc, J. Blondellc, R. Baets, P. Dcmcester, P. Van Dacle, G. Borglis, "High effcicncy planar microcavity LED's : comparison of design and experiment", IEEE Photonics Tcchnology Lctters, ISBN 1041-1 135/95, Vol. 7,Nr. 3, March 1995, pp. 287-289. IU R. Bockstaele, et al.", Realisation and Characterisation of 8x8 Resonant Cavity LED arrays mounted onto CMOS drivers for POF based interchip intcrconnections", IEEE Journ Scl. Top. Quant. Eleclr, MarchiApril 1999, Volume 05, Numbcr 02. II A. Neyer, B. Wittmann, and M. Johnck. "Plastic-OpticalFiber-Based Parallel Optical Interconnects", lEBE journal of sclected topics in quantum electronics MarchiApril 1999, Volume 05, Number 02 J.P. Hall, et al.,'Packaging of VCSEL, MC-LED and Detector 2-D Arrays', proceedings of48"' ECTC, May 2528. 1998

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