Two-dimensional analysis of emitter resistance in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 9, SEPTEMBER 1992

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Two-Dimensional Analysis of Emitter Resistance in the Presence of Interfacial Oxide Breakup in Polysilicon Emitter Bipolar Transistors John Starr Hamel, Member, IEEE, David J. Roulston, Senior Member, IEEE, C . R. Selvakumar, Member, IEEE, and G . R. Booker

Abstract-Two-dimensional (2D) computer simulations of the emitter resistance and majority carrier current flow in the presence of interfacial oxide breakup in polysilicon emitter bipolar transistors are shown and compared with published experimental results. The analysis reveals that the behavior of the emitter resistance with oxide layer breakup can be adequately predicted only if 2D majority carrier current flow is taken into account. Simulation of 2D majority carrier current flow and the resulting potential distribution in the emitter imply that the interfacial layer plays an important role in determining the emitter resistivity only in the very early stages of oxide layer breakup when the total gap area comprises an extremely small percentage of the interface. Both existing experimental data and theoretical 2D analysis reveal a much faster fall-off in emitter resistance with oxide layer breakup than previous one-dimensional theoretical analyses have suggested. In light of previous experimental measurements of gain fall-off as a function of interfacial oxide layer breakup, the 2D majority carrier modeling presented here suggests that the emitter resistance decreases much more rapidly than the current gain in the early stages of oxide layer breakup. Physical mechanisms which explain the differences in the dependence of the emitter resistance and gain on oxide layer breakup are proposed.

I. INTRODUCTION LYCRYSTALLINE silicon technology has been largely responsible for the reductions in the size of bipolar transistors enabling the use of bipolar technology in Very Large Scale Integration (VLSI) applications. A crucial step is the fabrication of polysilicon emitter transistors in the clean treatment of the monosilicon surface prior to deposition of the polysilicon. It has been shown [ l ] that a thin interfacial oxide layer formed by the interfacial clean can act as a tunneling bamer for camers in the polysilicon emitter transistor. Besides presenting a barrier to minority camer transport, thereby suppressing minority camer transport from the base to the emitter and enhancing the dc current gain, the interfacial layer can

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Manuscript received October 18, 1991; revised March 23, 1992. This work was supported by NSERC, IODE, and MICRONET, Canada. The review of this paper was arranged by Associate Editor A. H. Marshak. J. S. Hamel, D. J. Roulston, and C. R. Selvakumar are with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont., Canada N2L 3G1. G. R. Booker is with the Department of Materials, University of Oxford, Oxford, UK. IEEE Log Number 9201839.

also impede the flow of majority carriers giving rise to an emitter series resistance component which can dominate the overall emitter resistance [2]. The effect of this interfacial layer on emitter resistance has been quantitatively studied [3]-[6] and it has been determined experimentally from these studies that the oxide layer can represent the dominant component. As the emitter area is progressively decreased in small-geometry VLSI bipolar transistors, the emitter resistance necessarily increases and can adversely affect the performance of VLSI bipolar integrated circuits if it becomes large. Emitter resistances of several hundred ohms can result in present VLSI devices with interfacial oxide layers, whereas resistances of over 100 Q can adversely affect both analog and digital bipolar circuits [7], thereby seriously limiting the usefulness of polysilicon emitter bipolar transistors in VLSI applications. Fortunately, it has been found [8]-[lo], [12], [13], [18] that the interfacial oxide can be broken up or “balled up” to varying degrees by thermal annealing, bringing about epitaxial regrowth which reduces emitter resistance considerably. Detailed high-resolution transmission electron microscopic (HRTEM) examination of the interfacial oxide layer has made it possible to relate the amount of oxide layer breakup directly to process annealing conditions and to transistor electrical characteristics [3], [ 113, [12]. At the present time, in order to yield devices in which the gain is reproducible, it is generally considered necessary to either leave the oxide interface intact or to completely ball up the interface layer consequently inducing epitaxial alignment of the polysilicon layer with the underlying monocrystalline substrate. The former approach will yield devices with enhanced gain resulting from base current suppression, but with relatively large emitter resistances if the emitter geometry is relatively small (i.e., emitter area less than 2 pm2) [7]. The complete breakup of the interface oxide layer will eliminate most of the emitter resistance, but at the expense of a significant loss in gain enhancement which resulted from the intact interface layer in the first place. Since enhanced gain may be traded off for a higher base doping resulting in a reduced base resistance and higher maximum oscillation frequency (fmax), it is desirable to find optimum processing conditions which will yield the best tradeoff

0018-9383/92$03.00 0 1992 IEEE

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between gain enhancement and emitter resistance by inducing only partial breakup of the oxide layer while still retaining reproducibility in gain and emitter resistance. One-dimensional studies [3], [ 111, which ignore lateral flow in the emitter, fail to adequately model the effect of the interfacial layer breakup on the emitter resistance. It has been shown recently [ 141 that two-dimensional current flow must be considered to properly account for the observed dependence of the emitter resistance on the extent to which the interfacial layer has been broken up. OF THE Two11. NUMERICAL CALCULATION DIMENSIONAL EMITTERRESISTANCE Two-dimensional (2D) computer simulations of the emitter resistance are based on a typical polysilicon emitter as shown in Fig. 1, where the contributions of metal contact resistance R,,, the polysilicon resistance R,,,, the interface resistance Rinterface,and the monocrystalline emitter resistance R,,,, to the overall emitter resistance R, are included in a 2D resistor grid network (Fig. 2). Also, realistic elliptically shaped oxide segments are assumed, consistent with HRTEM observations [ 121, such that oxide volume is conserved during oxide layer breakup. All regions of the emitter-Gaussian-doped monosilicon region with position-dependent mobility, oxide layer with gaps, and a uniformly doped polysilicon region-are represented by a two-dimensional resistor grid network. To model oxide breakup, several uniformly distributed gaps of equal size are assumed whose size depend upon the preanneal conditions. Finally, the resistor network was analyzed by the circuit network simulator, WATAND [15], from which the 2D majority carrier current and potential distributions, and consequently, the overall specific emitter resistivity were determined. Two methods are used to calculate the overall effective emitter resistance once the 2D emitter resistance grid is formed. Both methods involve the initial assumption of a uniform majority carrier emitter current at the emitterbase space-charge edge of the monoemitter region along the entire width of the emitter diffusion. The voltage drop at each node in the 2D resistor grid is then determined using WATAND. In general, if there is significant lateral flow in the 2D resistor network because of the presence of gaps or low-resistance paths in the oxide interface layer, then the voltage distribution along the width of the emitter region at the edge of the emitter-base space-charge layer will be nonuniform. This nonuniform voltage distribution will in turn cause a variation in the forward bias along the width of the emitter, which in turn will result in a variation in the majority carrier current injected along the emitter width. The new currents at each input node to the emitter are then adjusted according to the voltage drop at each node by

The voltages at each node are recalculated and the cur-

r/rX

-w

POLY

A k X i e b

4

LDEL n

Fig. 1 . Vertical emitter structure used for modeling emitter resistance in presence of interfacial layer breakup.

pow-

r.a.: :m: . . :m: . . . :a . . .

Rlla . . . . .

L

LATERAL WIDTH OF SECTION

Fig. 2. Two-dimensional resistor grid network corresponding to a vertical cross section containing one gap in the emitter.

rents readjusted until the system converges. Once the actual majority carrier current and voltage distribution along the emitter width is determined, the effective emitter resistance can be calculated by

lrnew

where I, old is the total uniformly distributed majority carrier current originally assumed to be injected into the emitter, and I,,,, is the decreased total majority carrier current once the correct current and voltage distributions have been determined by iteration. This method is equivalent to applying a forward voltage V,, to the emitterbase junction to obtain an emitter current in the forward active region of operation assuming that the emitter series resistance is zero. After iterating to find the correct current distribution, the total collector current will be less than the originally assumed value that corresponded to V,, by an amount of exp ( - V E / V,) where V, is the overall voltage drop over the emitter series resistance. From V ,

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one can easily obtain the effective emitter series resistance. It is assumed that the lateral voltage drops in the transverse base are negligible, although this effect can be included. Because the experimental results were obtained from devices [3] where it was determined that emitter current crowding was negligible, this effect was neglected in the emitter resistance calculations. Alternatively, once the correct current and voltage distributions have been obtained, power dissipation considerations can be used to determine the emitter resistance by applying each node current separately and determining the corresponding node voltage. The resistance is then given by

5oo

1

OXIDE UYER THICKNESS = 1 1 A'

~ E M I T T E RAREA

6r6 #d

0.01 pm ?SAL CONTACT RESISTANCE

A

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L

L

D

EXPERIMENTAL POINTS

C I ( i )V ( i ) Re=

(3) Itnew

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500 GAPS

-/

Both approaches yield essentially the same results. AND 111. EMITTERRESISTANCE CALCULATIONS COMPARISON WITH EXPERIMENT In this section comparisons are made between 2D numerical calculations and existing experimental measurements [3] of specific emitter resistivity as a function of the percentage of oxide remaining along the length of the interface, the detailed processing of the measured devices being described in 131, [12]. Fig. 3 shows a comparison between calculated emitter resistivity and two measured results in the very early stages of oxide layer breakup. It should be emphasized that the results shown are plotted as a function of the percentage of oxide remaining along the length of the interface in a vertical cross section of the emitter as determined by HRTEM cross-sectional analysis. The percentage of oxide area is then assumed to be roughly the square of the percentage along the interface length. In order to model the majority carrier current flow, and thereby determine the specific emitter resistance as a function of the pre-anneal temperatures and the extent of oxide breakup, the spacing and hence the number of gaps which exist in the oxide layer had to be taken into account. Based on the HRTEM observations, for the devices used in the resistance measurements of [3], it was estimated that at least 50 gaps existed along a given length of a vertical section of the interfacial layer. Fig. 3, therefore, shows comparisons between calculated emitter resistances for various percentages of remaining oxide and the number of gaps in the oxide layer. It can be seen that for greater than 50 gaps, there is little change in the behavior of the emitter resistance with oxide layer breakup. The dramatic effect of varying the number of gaps on the emitter resistance, for a given percentage of oxide remaining, can be clearly seen. Even though the amount of oxide breakup, corresponding to a particular pre-anneal temperature, remains fixed, the effect of increasing the mere number of gaps is to reduce the emitter resistance, even though the total gap area remains constant. It is apparent from these simulations that the emitter series resis-

__

tance not only depends upon the ratio of gap area to intact oxide area, but also depends strongly upon the distribution of the gap area for a given amount of oxide layer breakup. The most striking behavior, regarding the experimental results, is the large decrease in emitter resistivity from the control to the 900°C sample for what appear to be conditions where the oxide layer has not yet begun to break up (i.e., 100%oxide along the interface). Indeed, HRTEM observations [12] reveal that the oxide layer was unaffected by the 900°C pre-anneal and emitter drive-in, with no change in uniformity or thickness. Emitter resistance measurements [3] reveal that this decrease cannot be attributed to a decreases in the other emitter resistance components (i.e., Rpoly,R,,,,, and Itmc)since these resistances, in total, are less than the difference in emitter resistance between the control and the 900°C samples. Therefore, some change must have taken place in the interfacial oxide layer to account for the reduction in emitter resistivity. Comparison between calculations and measurements of emitter resistance versus current [3], however, for the 900°C pre-anneal sample suggests >hat a thinning of the oxide layer to approximately 10 A is responsible for the large reduction in emitter resistivity. If this were true then some of the oxide would have to disappear from the interface entirely which is inconsistent with the observation that the oxide volume appeared to remain constant even to complete balling-up for the 1100°C pre-anneal sample [ 121. Therefore, the only reasonable explanation for the rapid reduction in emitter resistance is the formation of numerous, extremely small gaps in the oxide layer that, in total, comprise a very small area of the interface. The simulation results suggest that a reduction in emitter resistance of this magnitude, be-

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6

Fig. 4. Two-dimensional potential distribution in the emitter for RCA ( 1 1 A ) oxide layer and monoemitter width of 0.01 pm, where (a) I gap and (b) 50 gaps exist along the interface length. The total oxide gap area is constant at 1 % for all cases. (c) Potential distribution for the same device but where all the oxide has been completely balled-up. (A depth of 0 corresponds to the emitter metal contact with the deepest part of the emitter being at the emitter-base space-charge edge of the monoemitter quasi-neutral region.)

tween the control and the 900°C sample, can occur if the bution of the potential distribution which arises from matotal sum of all the gaps is even less than 2 % of the in- jority flow in the emitter in the presence of oxide layer terface length (which corresponds to the gaps comprising breakup. Fig. 4 shows the spatial potential distribution for the roughly only 0.04% of the entire interface area) provided there is a sufficient number of uniformly distributed gaps. same device u!ed for the emitter resistivity calculations It is possible that HRTEM observations carried out in [ 121 in Fig. 2 (1 1 A oxide and Xi, = 0.01 pm). Going from did not detect such small gaps making the oxide layer ap- Fig. 4(a) to Fig. 4(b) the number of oxide gaps along pear continuous. the length of the interface is increased from 1 to 50 where the total gap area is assumed to comprise only 10% of the IV . TWO-DIMENSIONAL POTENTIAL DISTRIBUTIONS DUE length of the interface. This would correspond to a total TO MAJORITY CARRIER TRANSPORT IN THE EMITTER gap area of roughly 1% of the total oxide interface area. In order to obtain a physical explanation for the strong In Fig. 4(a) it can be seen that one gap in the center independence of the emitter resistance on the extent of ox- duces significant lateral voltage drops in the monoemitter ide breakup, it is useful to analyze the 2D spatial distri- region (towards the back of the figure). Conversely, in

HAMEL et al.: ANALYSIS OF EMITTER RESISTANCE IN POLYSILICON EMITTER BIPOLAR TRANSISTORS TOTAL LATERAL PATH LENGTH

6P

j

211

L,_I_f_I_I-f-J Fig. 5. Schematic of the interfacial layer depicting the dependence of the total lateral path length of the majority camer emitter current on the number of gaps for a constant total gap area.

Fig. 4(b), where 1 section containing 1 of 50 gaps along the interface length is shown, the breaks in the oxide appear to induce little or no significant vertical or lateral voltage drops in the monoemitter region, the end result being a much smaller overall voltage drop across the entire emitter and hence a greatly reduced emitter series resistance. Indeed, comparing Fig. 4(b) and (c), where no interfacial oxide was assumed to be present in Fig. 4(c), the potential distribution, and consequently the overall total voltage drop across the emitter, is nearly the same. From Fig. 4 it is clear that the distribution of an extremely small total oxide gap area (in this case a mere 1%) into a large number of small gaps has nearly the same effect as the total breakup or elimination of the interfacial oxide layer. The 2D potential distributions (especially Fig. 4(b) and (c)) provide a convincing argument that the interfacial oxide layer influences the emitter resistivity only in the very early stages of oxide layer breakup and that other sources of emitter resistance must dominate for larger percentages of breakup. From the 2D potential distributions a simple physical explanation can be derived for the strong dependence of emitter resistance on the number and distribution of oxide layer gaps. For an extreme case of only one gap in the center of the interfacial layer, the majority carrier current flow, which originates at the emitter-base junction on the right, is diverted laterally towards the relatively low resistance path in the gap. This lateral flow gives rise to sizable ohmic voltage drops since the lateral sheet resistance in the ultrathin monocrystalline silicon emitter is large. In the other extreme, with many smaller gaps distributed uniformly throughout the interfacial layer, there is a significant reduction in total lateral current flow resulting in a substantial overall reduction in the emitter resistance since the current has less distance to travel laterally through the monoemitter to reach a gap. Fig. 5 illustrates this with a simple example, showing that the total lateral path length of current elements is reduced from 61 to 2.51 if the number of gaps is increased by 4 , but where the total gap area remains constant.

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V. TRADEOFFBETWEENEMITTERRESISTANCE AND CURRENT GAIN

In Fig. 6 are plotted experimental measurements of base saturation current [ 121 and emitter resistivity [3] versus interfacial oxide layer breakup for the same device from which the data were obtained for Fig. 3 (xJeb = 0.01 pm, RCA oxide), where the data from Fig. 3 for the emitter resistivity have been repeated to facilitate comparison, and emitter resistivity value for 0% oxide layer was obtained from an estimate based on data from [3] as well as 2D simulations. From this figure it appears that the largest tradeoff between current gain and emitter resistance would be expected to occur in the very early stages of oxide layer breakup. Clearly, these data imply that a dramatic reduction in emitter resistance can be obtained with very little increase in base saturation current if the extent of the oxide layer breakup is brought just to, or slightly beyond the transition point where the interfacial layer no longer dominates the emitter resistance. The physical mechanisms governing the behavior of the emitter resistance in the early stages of oxide layer breakup have already been discussed in detail; however, it is not obvious why there is little change in the base saturation current in this regime. Although it has been established experimentally that there is a significant difference in the tunneling probabilities for holes and electrons through the thin interfacial oxide layer [12], there is no reason to believe that holes are preferentially suppressed with respect to electrons passing through the gaps. Furthermore, the mean distance that a hole would have to diffuse to reach a gap is considerably less than a hole diffusion length if there are a sufficient number of gaps. For example, it was determined for the structures considered in this work, that at least 50 gaps had to exist along the interface length to realize the observed fall-off in emitter resistance which corresponds to a gap separation of 0.12 pm compared with a hole diffusion length of 0.48 pm for ~ .reala monoemitter surface doping of 8 X 1019 ~ m - In ity, the distance between gaps may be even less than this if there were many more gaps than the minimum estimated. From Fig. 4(b), showing the 2D potential distribution for 50 gaps comprising 10% gap along the interface length, and Fig. 4(c) where there is no oxide for the entire emitter interface, it is clear that if the number of gaps is large enough, there are virtually no lateral potential drops along the plane of the interface between gaps as a result of the diverted majority carrier flow, thereby implying that there is no appreciable drift component of hole current towards the gaps as suggested in [ 111. Lateral minority camer flow towards the gap would then be driven only by concentration gradients between higher hole concentrations adjacent to intact oxide and lower concentrations adjacent to gap areas. From the 2D analysis of majority carrier flow, it can be concluded that the majority carriers are driven through the gaps by pure drift and the minority carriers by diffusion. A further fundamental difference exists between the

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-

RW OXIDE X+ 0.01 pn

BASt SATURATlOh CURRENT

W

P n -. , "

0

20

40

60

80

100

PERCENTAGE OF INTERFACE WITH OXIDE ALONG LENGTH OF INTERFACE (%)

Fig. 6 . Experimental measurements of base saturation current [12] and specific emitter resistivity [3] versus percentage of oxide remaining along the length of the interface for an RCA oxide and monoemitter width of 0.01 pm.

majority and minority carrier flows in the emitter. The mechanisms which determine the magnitude of the majority and minority carrier currents are essentially decoupled. The magnitude of the majority current in the emitter is determined by the base Gummel number and can be thought of as being forced through the gaps in the oxide layer, whereas the minority carrier current in the emitter is determined by boundary conditions in the emitter itself. Hence, it is reasonable to assume that the oxide layer breakup will have a much different effect on minority carrier transport, which determines the gain, than it has on the majority carrier transport, which determines the emitter resistance. If there were no lateral minority carrier flow induced by the oxide gaps, one would expect to be able to determine the base saturation current 1161 from (4)

where Nd(w)is the emitter concentration at the base-emitter depletion region edge, and Se, is an effective recombination velocity which incorporates the various mechanisms responsible for base current injected into the emitter such as recombination at the interfacelmonoemitter boundary, tunneling through the oxide layer, and recombination in the polysilicon [ 121, and which is given by

se,

=

Ail A,,

Ani/ Ae w

s;/ - + s, -

where Si,is the effective recombination velocity for holes adjacent to intact oxide layer segments comprising the total area of Ail, S, is the effective recombination velocity for holes adjacent to gaps comprising a total gap area to A,;/, and where A,, is the emitter window area. This approach was attempted by Wolstenholme [ 171. For an extremely small total gap area that is sufficient to induce a substantial reduction in emitter resistance, as shown in Fig. 6, the ratio A i l / A e , is very close to unity and A n i l / A , ,

is very close to zero which results in a negligible change in Se, from the lower value of Si,.Since this approach appears to predict the observed behavior of the base saturation current for very small amounts of oxide layer breakup, it is reasonable to conclude that the lateral hole diffusion current in the plane of the interface between areas of high and low hole concentration must be only a small fraction of the total vertical hole current in the emitter. At least in the early stages of oxide layer breakup, it appears that the hole current is still essentially one-dimensional in nature and is little affected by the extremely small gaps. The mechanisms governing minority carrier transport in the presence of oxide layer breakup for the entire range from a uniform layer to complete balling-up can only be determined from full 2D minority carrier analysis, however, comparison of the 2D majority carrier modeling and experimental results provides useful insight into the these mechanisms, at least in the early stages of oxide layer breakup

VI. NEW EXPERIMENTAL DATA During the time that this paper was being reviewed for publication, new experimental data have been published [20] that confirm the central results of this paper. In this new work [20], the experiments of Wolstenholme et al. [3], [12] were repeated with a concentrated effort placed on observing the tiny gaps in the RCA oxide layer that were predicted in 1141. Indeed, these small gaps were observed and Fig. 7(a) shows the behavior of the emitter resistance as a function of the areal percentage of oxide layer breakup as presented in [20]. Fig. 7(b) shows the same numerically calculated emitter resistance of Fig. 3 replotted for areal percentage of oxide breakup (i.e., the square of the percentage of interface length without oxide). The initial oxide layer thickness for the data show! in Fig. 7(a) was measured to be on the order of 15 A [2016 while the calculations in this paper are for an 11-A interfacial layer. Except for the higher initial value of emitter resistance in Fig. 7(a) due to the thicker oxide layer, the overall behavior very closely resembles the behavior predicted by the numerical simulations. Furthermore, the ' 'oxide-free'' specific emitter resistivity for the new data is nearly the same as that for the devices of 131, [12]. Emitter resistance versus current gain was also assessed in [20] and it was experimentally determined that the best tradeoff between the two could be obtained for a real oxide layer breakup of 1 to 2%-a result which is numerically consistent, both with the 2D calculations and the experimental data presented in Fig. 6 of this paper. Finally, the emitter resistance-base saturation current product is seen not to be a constant, contrary to previous predictions [19], using the new data of [20], but rather behaves in a similar fashion to the data of [3], [ 121. VII. CONCLUSIONS The effects of 2D majority carrier current flow must be included to properly account for the observed dependence of emitter resistance on the extent of interfacial layer

HAMEL

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ANALYSIS OF EMITTER RESISTANCE IN POLYSILICON EMITTER BIPOLAR TRANSISTORS

500

> r, E

,A

1

I

EXPERIMENTAL POINTS

OXlOE LAYER THICKNESS = 1 1 A’ Xiab = 0.01 p m METAL CONTACT RESISTANCE

4001

that are sufficient to eliminate most of the interfacial layer component of the emitter resistance. Specifically, a 1% oxide gap area distributed into some 2500 gaps in a 6 X 6 pm emitter results in a very small loss in gain while most of the emitter series resistance associated with the oxide layer has been eliminated. Computed 2D potential distributions indicate that if there are a sufficient number of gaps in the interfacial layer, the lateral minority camer current in the plane of the interface is dominated by diffusion current which, in light of the observed dependence of gain on oxide layer breakup, must comprise only a small fraction of the total minority carrier current for small percentages of oxide layer breakup. Newly available experimental data indicate that indeed the creation of numerous small gaps in the interfacial layer in the early stages of oxide layer breakup can eliminate most of the resistance associated with the interfacial layer, providing further confirmation of the theoretical predictions derived from 2D majority carrier simulations.

0 - p d

-40

SIMULATION POINTS

ACKNOWLEDGMENT The authors wish to thank Dr. P. Ashbum of the University of Southampton for providing essential information regarding the experimental data used in this paper, and Dr. D. Gold for providing early access to his HRTEM results.

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50 GAPS ALONG 6.0 pm INTERFACE LENGTH

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REFERENCES 25

TOTAL AREAL PERCENTAGE OF OXIDE GAPS ( X )

(b) Fig. 7. Specific emitter resistivity as a function of areal percentage of oxide layer breakup from (a) experimental measurements of Liu et al. [21] for an initially 15-A-thick interfacial layer, and (b) from two-dimensional numeriSal simulations taken from Fig. 3 for an initial oxide layer thickness of 11 A .

breakup in polysilicon emitter bipolar transistors. Comparison between 2D analysis and experimental data suggests that grain boundaries incident upon the interfacial layer form extremely small perforations, which could be easily missed by HRTEM observations, at the initial stages of annealing, before growing in size as the layer breakup progresses. The analysis predicts that these small perforations, should they actually exist, could easily be responsible for the significant reduction in the emitter resistance observed experimentally. 2D potential distributions in emitters with partially broken up oxide interfacial layers suggest that the distribution of an extremely small percentage of oxide gap area into a sufficiently large number of small gaps can result in a series emitter resistance which is comparable to that which could be obtained if the oxide layer were to be completely balled-up or otherwise removed. Previous experimental measurements of current gain versus oxide layer breakup indicate that there is only a small reduction in gain for percentages of oxide gap area

[ I ] H. C. deGraaf and J. G. deGroot, “The SIS tunnel emitter: A theory for emitters with thin interfacial layers,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1771-1776, Nov. 1979. [2] P. Ashbum, D. J. Roulston, and C. R. Selvakumar, “Comparison of experimental and computed results on arsenic and phosphorous doped polysilicon emitter bipolar transistors,” IEEE Trans. Electron. Devices, vol. ED-34, pp. 1346-1353, 1987. [3] G. R. Wolstenholme, P. Ashbum, N. Jorgensen, D. Gold, and G. R. Booker, “Measurement and modelling of the emitter resistance of polysilicon emitter transistors,” in IEEE BCTM, 1988, pp. 55-58. [4] E. F. Chor, P.Ashburn, and A. Brunnschweiler, “Emitter resistance of arsenic- and phosphorous-doped polysilicon emitter transistors,” IEEE Elecrron. Device Lett., vol. EDL-6, pp. 516-518, 1985. [5] P. A. Potyraj and D. W. Greve, “Emitter resistance in polysilicon emitter transistors and the influence of interfacial oxide,” in IEEE BCTM, 1987, pp. 82-85. [6] Y. Niitsu, M. Norishima, G. Sasaki, H. Iwai, and K. Maeguchi, “Comparison between poly emitter bipolar characteristics with and without native oxide layers under various processes,’’ in IEEE BCTM, 1989, pp. 98-101. [7] T. Yamaguchi, Y-C. S . Yu,V. Drobny, and A. Withouski, “Emitter resistance and performance trade-off of submicrometer self-aligned double-polysilicon bipolar devices,” in IEEE BCTM, 1988, pp. 5962. [8] B. Y. Tsaur and L. S . Hung, “Epitaxial alignment of polycrystalline Si films on (100) Si,” Appl. Phys. Lett., vol. 37, pp. 648-651, 1980. [9] J. L. Hoyt, E. Crabbe, J. F. Gibbons, and R. F. W. Pease, “Epitaxial alignment of arsenic implanted polycrystalline silicon films on ( 100) silicon obtained by rapid thermal annealing,” Appl. Phys. Lett., vol. 50, pp. 751-753, 1987. IO] J. C. Bravman, G. L. Patton, and J . D. Plummer, “Structure and morphology of polycrystalline silicon-single crystal silicon interfaces,” J. Appl. Phys., vol. 57, pp. 2779-2782, 1985. 111 D. Gold, Doctor of Philosophy Dissertation, Oxford University, Oxford, UK, 1989. 121 G. R. Wolstenholme, N Jorgensen, P. Ashbum, and G. R. Booker, “An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device

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results with high-resolution electron microscopy observations,” J . Appl. Phys., vol. 61, pp. 225-233, 1987. [I31 T. Maeda, M Higashizona, H. Momose, and J. Matsumaga, “Poly Si-Si interfacial oxide ball-up mechanism and its control for 0.8 pm BiCOMOS VLSI’s,” in IEEE ECTM, 1989, pp. 102-105. [I41 J. S. Hamel, D. J. Roulston, P. Ashbum, D. Gold, and C. R. Selvakumar, “2-D computer simulation of emitter resistance in presence of interfacial oxide break-up in polysilicon emitter bipolar transistors,” presented at the 20th European Solid State Device Research Conf., Sept. 1990. [I51 I. Hajj, K. Singhal, J. Vlach, and P. Bryant, “WATAND-A program for the analysis and design of linear and piecewise linear networks,” in Proc. 16th Midwesfern Symp. on Circuit Theory (Waterloo, Ont., Canada 1973). [I61 Z. Yu, B. Ricco, and R. W. Dutton, “A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 773-784, June, 1984. [I71 G. R. Wolstenholme, Ph.D. dissertation, University of Southampton, Southampton, England, 1988. [I81 G. L. Patton, J. C . Bravman, and J. D. Plummer, “Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors,” IEEE Trans. Elecrron Devices, vol. ED-33, pp. 17541768, Nov. 1986. [I91 L. M. Castaner, P. Ashbum, and G. R. Wolstenholme, “Effects of rapid thermal processing on the current gain and emitter resistance of polysilicon emitter bipolar transistors,” IEEE Electron Device Lerr., vol. 12 pp. 10-12, Jan. 1991. [20] T. M. Liu, Y. 0. Kim, K. F. Lee, D. Y. Jeon, and A. Ourmazd, “The control of polysilicon/silicon interface processed by rapid thermal anneal,” in IEEE BCTM, Sept. 1991, pp. 263-270.

John Starr Hamel (S’89-M’92) was bom on Pelee Island, Ont., Canada, on November 14, 1959. He received the Bachelors of Engineering degree in engineering physics from the Royal Military College of Canada in 1982. After finishing his tour of duty with the Canadian Air Force, he completed the Master of Applied Science (August 1989) and the Ph.D. (January 1992) degrees in electrical engineering at the University of Waterloo, Waterloo, Ont., where he is presently a Post Doctoral Fellow in the Department of Electrical and Computer Engineering. From 1982 to 1987 he served as a pilot and an officer in the Canadian Air Force. In 1986 he was attached to the Multi-National Force and Observers (MFO) in the Middle East to carry out peace-keeping duties which involved flying reconnaissance missions in the Sinai desert. His current research interests involve the modeling and fabrication of VLSI bipolar devices, including polysilicon emitter and SiGe heterojunction bipolar transistors, and multidimensional dc, ac, and transient device simulation. He is a recipient of an IODE (Imperial Order Daughters of the Empire) War Memorial Scholarship.

David J. Roulston ( ~ ’ 6 2 - ~ ~ ’ 7was 2 ) born in England in 1936. He received the B.Sc. degree from Queen’s University, Belfast, N. Ireland, in 1957, and the Ph.D. degree from Imperial college, University of London, London, England, in 1962. From 1957 to 1958 he was a Scientific Officer at H. M. Underwater Detection Establishment, Portland, Dorset, England. From 1962 to 1967 he was a research engineer with CSF, Puteaux, France, working on microwave semiconductor circuits. In 1967 he became an Associate Professor with the Department of Electncal Engineenng, University of Waterloo, Waterloo, Ont., Canada, and since 1971 he has been a Professor with the same department. He has

also held consulting positions with R&D laboratories in Canada, France, Japan, USA, and with UNIDO in India. His research interests are in modeling physical processes in semiconductor devices: specifically, bipolar transistors (including microwave, high-voltage, and VLSI structures), microwave diodes, photodiodes, MESFET’s and in studying discrete and integrated circuits with a view to the optimization of device performance for a particular circuit function. This work involves both experimental and computer techniques. He is responsible for development of the BIPOLE computer program for analysis of bipolar devices. He has published over 100 technical papers in the above fields and has had 6 patents awarded in the areas of microwave and optical detector circuits and bipolar devices. He has presented invited seminars or conference papers in twelve countries. He is co-editor of the IEEE PRESS book Polysilicon Emirrer Bipolar Transisrors and author of the McGraw-Hill graduate text Bipolar Semiconducror Devices. Dr. Roulston is a Fellow of the Institution of Electrical Engineers (England). He was Associate Editor for Bipolar Devices of the IEEE TRANSACTIONS ON ELECTRON DEVICES for two years and is currently on the Honorary Editorial Advisory Board of Solid Stare Elecrronics. For the academic year 1988-1989 he was elected a Visiting Fellow at Wolfson College, Oxford.

C. (Selva) R. Selvakumar (S’80-M’86) was bom in Karur, Tamil Nadu, India, on March 17, 1950. He received the B.E. degree in electrical engineering from College of Engineering, Guindy, Madras, in 1972, the M.Tech degree in electrical engineering from Indian Institute of Technology, Bombay, in 1974, and the Ph.D. degree from I.I.T. Madras in 1985. He was one of the first developers of a microwave p-i-n diodes for Phased Array Radar application in India in 1973. His Ph.D. work was based on a new analytical approach to solve semiconductor device equations in heavily and non-uniformly doped regions. His interests are in analytical modeling and generic approaches. From 1975 to 1978, he was a Research Scholar at I.I.T. Madras and was partly responsible for setting up the Microelectronics Device Laboratory. From 1978 to 1984, he was leading two research projects as a Project Associate at I.I.T. Madras. One of the projects involved the development of ultrasensitive photo p-i-n diodes for UV, visible, and IR radiation, sponsored by the Department of Science and Technology, Govemment of India, and the other project was on lifetime control using platinum for high-speed switching devices sponsored by Bharat Heavy Electrical Limited. From 1985 to 1987, he was with the Department of Electrical Engineering, University of Waterloo, Waterloo, Ont., Canada, as a Postdoctoral Fellow working on the physics, technology, and modeling of polysilicon emitter bipolar transistors. Since the Fall of 1987, he has been with the Department of Electrical and Computer Engineering, University of Waterloo as an Assistant Professor. In the Winter 1992 he was a Visiting Assistant Professor in the Department of Electrical Engineering at Stanford University Stanford, CA, for three months. In 1989 he contributed a review article on Polvsilicon Emitter BiDolar Transistors which appears in the IEEE PRESS bodk Polysilicon Emitier Bipolar Transzsrors edited by A. Kapoor and D J. Roulston. His current research interests are in bipolar transistors, SiGe channel MOSFET’s, vertical polysilicon emitter bipolar transistors on SOI, and novel group IV binary and temary alloy devices and quantum effect devices. Dr. Selvakumar is a member of the Technical Program Committee of IEEE Bipolar Circuits and Technology Meeting. He is a Chairman of the Kitchener-Waterloo IEEE Section Electron Devices, Circuits and Systems Chapter. He has been an Associated Key Researcher of the Provincial Centre of Excellence (ITRC) since 1991. He is cited in American Men and Women of Science 1992 edition. He is a member of AIP and MRS.

G. R. Booker, photograph and biography not available at the time of publication.