Simplified high-efficiency silicon cell processing

SAND93-1435C Presented at the 7th International PhotovoltaicScience and Eiigineering Conference, Nagoya, November 1993

Simplified High-Efficiency Silicon Cell Processing Paul A. Basore, James M. Gee, M. Elaine Buck, W. Kent Schubert, and Douglas S . Ruby Sandia National Laboratories, Albuquerque New Mexico 87185 USA ABSTRACT

We developed an emitter diffusion process that yields a nearideal doping profile with a passivating oxide in a single furnace step. Because this process subjects the material to only one hightemperature thermal excursion, bulk lifetime is better preserved. This is especially true for lower-cost silicon materials containing a high concentration of oxygen or carbon. Using this process, we routinely obtain one-sun cell efficiencies over 19% on float-zone material and over 18% on Czochralski material. Using solar-grade Czochralski material, we have demonstrated record efficiencies of 17.6% at one sun and 20.0% under concentration. Simple processes that yield high-performancediffusion profiles are expected to become increasingly important as manufacturers adopt improved techniques for ohmic contacts.

1. Introduction The primary objective of the Photovoltaic Device Fabrication Laboratory at Sandia National Laboratories is to develop processes that improve the performance, reduce the cost, and minimize the environmental impact of fabricating silicon solar cells on an industrial scale for terrestrial applications. Obtaining high efficiency with any material requires excellent passivation of surfaces as well as high bulk lifetime. Excellent front-surface passivation can be obtained using a light phosphorus diffusion covered by a thermally grown layer of silicon dioxide. We successfully fabricated high-efficiency cells on solar-grade wafers by developing a relatively simple fabrication sequence that requires only one furnace process above 800°C. Heavily doped emitters significantly reduce the response of commercially fabricated silicon solar cells to the blue end of the solar spectrum. There are two reasons why commercial cells suffer this limitation, which is not encountered in highperformance laboratory cells. (1) High surface doping density is needed in commercial cells to reduce contact resistance to screenprinted gridlines. (2) The single-step furnace process used in industry inherently produces a high surface doping density, equal to the solid solubility of the dopant at the temperature of the diffusion process. To obtain an adequatejunction depth in a short period of time, the diffusion process is performed at a temperature above 850°C. At these temperatures, the solid solubility of phosphorus in silicon is greater than 5 x 1020 ~ r n - Such ~ . heavy doping interferes with surface passivation, as well as introducing excessive bulk recombination within the emitter. Heavy doping may be necessary to permit good ohmic contact to l o w e s t metallization, but it does not have to hurt a cell's blue response, if the heavy doping can be restricted to areas covered by metal. Examples include buried-contact cells /l/, etched-back emitters 121, and designs that put the contacts on the rear surface /3/, Each of these options is under development to make them This work performed at Sandia National Laboratories is supported by the US Department of Energy, contract DE-ACO4-76DPOO789.

more economically attractive. As one or more of these approaches become more prevalent in industsy, it will be important to have a simple process for producing a lightly doped emitter at the front surface of the cell. Until the commercial need for lightly doped emitters emerges, cells using more sophisticated contacting technology can benefit immediately from a simplified process for producing the desired emitter doping profile. Evaporated metal contacts make good ohmic contact to surface concentrations as low as 1 x 1019 ~ m - We ~ . developed a method for making high-performance cells on a variety of silicon materials by combining evaporated metal contacts with a simple process for lightly doped emitters.

2. Initial Experience with POCl3 Diffusions Our first experiments with liquid POCl3 as a phosphorus dopant source in a tube furnace indicated that we could obtain very different sheet resistance for the same time and temperature, depending on whether the furnace ambient following the deposition of phosphorus glass was oxygen or nitrogen. We did not observe this effect using PH3 as the dopant source. Further investigation suggested that a nitrogen ambient allowed the POCl3 diffusion to proceed as expected, while an oxygen ambient interfered with the diffusion of phosphorus into the silicon, yielding much higher sheet resistance. For example, one sequence yielded 8 52/n with a nitrogen ambient but 100 RIP with oxygen. Our standard phosphorus diffusion process for 100-mmdiameter wafers uses a quartz tube furnace, quartz boats holding the wafers transverse to the gas flow, silicon-carbide cantilever paddles, and digital mass-flow controllers for all gases. As the wafers are pushed into the furnace, the temperature is held at 8OO0C,and the gas ambient is nitrogen. Once the paddle is fully loaded, the temperature is ramped up at S"C/minute to the desired process temperature. Once the process temperature is stabilized, the furnace ambient is switched to oxygen, and a small nitrogen stream is diverted through a temperature-controlledPOCl3 bubbler to deliver dopant to the furnace at the rate of 200 mgminute. We call this the "deposition" step. The POCl3 oxidizes during this step, depositing P2O5 glass on the surface of the wafers and releasing chlorine gas which getters metallic impurities from the wafers and from the walls of the fwnace tube. At the end of the desired deposition time, the furnace ambient can be switched to nitrogen for what we call the "nitrogen soak" step. Phosphorus from the deposited glass diffuses into the silicon wafer during this step. At the end of the desired nitrogen soak time, the furnace ambient can be switched to oxygen for an "oxidation" step. AAer oxidation, the ambient is switched back to nitrogen for a 15-minute "in situ anneal" intended to reduce interface state density at the silicon surface. The temperature is then ramped down to 800°C at S0C/minute,and the wafers are unloaded from the furnace. When not in use, the furnace is held at 800°C, with flowing nitrogen. Each fwnace tube is cleaned in situ using TCA when it is first installed but is otherwise cleaned only infrequently, when the lifetime of test wafers indicates possible contamination.

Our first controlled experiment with POCl3 explored deposition times from 1 to 10 minutes, oxidation times from 10 to 100 minutes, and process temperatures from 800 to 1000°C. The nitrogen soak was omitted entirely from this experiment. We obtained sheet resistances ranging from 10 to 1000 RIP, but to our surprise, the sheet resistance was indemdent of the oxidation time! From this result we concluded that the diffusion of phosphorus from the doped glass into the silicon is shut off during the oxidation step.

4. Detailed Evaluation of II Baseline 900"C Process At a temperature of 900°C ,it is possible to obtain the following near-ideal emitter attributes from a single furnace process, making it ideal for fabricating simple yet efficient solar cells: 0 0 ' 0 0

3. POCI3 Diffusions with Short Oxidation Time We designed a follow-on experiment to characterize fully the most important parameter space for our diffusion process. Since oxidation time has no effect on the sheet resistance, we fixed the oxidation time at 10 minutes. A nitrogen soak was included with times ranging Erom 1 to 10 minutes. The experiment was designed as a fullquadratic response-surface factorial with three factors: The logarithm of the deposition time, the logarithm of the nitrogen soak time, and the diffusion-process temperature. The primary observables were the logarithm of the sheet resistance (measured using a four-point probe) and the thickness of the surface oxide (measured using ellipsometry). Figs. A-l through A-5, appended to this article, illustrate the sheet resistance that can be obtained using the one-step diffusion process at temperatures ranging from 850 to 950°C. Recall that while this data was generated using a short oxidation time, longer oxidation times can be used to drive the junction deeper and reduce the surface concentration without significantly affecting the sheet resistance. From these graphs it is apparent that the sheet resistance becomes quite sensitive to small process variations if the deposition time or the nitrogen soak time are less than about 2 minutes. Thus, while a given sheet resistance can be obtained over a wide temperature range, by varying the deposition and nitrogen soak times, the most robust and repeatable process corresponds to the lowest temperature at which the desired sheet resistance is achievable, This is consistent with our desire to keep the process temperature low to help preserve the bulk lifetime of the material. The sheet resistance and junction depth should be selected to combine excellent blue response with low emitter sheet resistance loss and low contact resistance loss, within the context of the specific gridline technology being used. A typical highperformance passivated front-surface emitter diffusion for one-sun operation has a sheet resistance of about 100 R R and a junction depth of about 500 nm. From Figs. A-l through A-5, this sheet resistance is most reliably obtained at 850 or 875OC. Desirable junction depths can be obtained at these temperatures by increasing the oxidation time to 1-3 hours. The thickness of the oxide resulting from the one-step diffusion with a short oxidation is illustrated in Fig. A d . The oxide thickness obtained is independent of the nitrogen soak time, which is to be expected since this step neither deposits nor grows an oxide. The thickness increase with either deposition time or temperature is approximately linear. Note that the 10-minute oxidation step grows some thermal oxide that is present even when there is little or no deposited P2O5 glass. For oxidation times longer than 10 minutes, the oxide thickness grows beyond the values shown in Fig. A-6. The presence of phosphorus at the silicon surface and in the oxide combine to accelerate the oxidation rate to about twice that obtained for dry oxidation of undoped wafers.

100 R/o sheet resistance 700-nm 'unction depth 3 x 10ld cm-3 surface concentration 70 E4/cm'2 Joe at 25°C (estimated 100 €4/cm-2 including 3% metal contact) 110-nm low-reflectanceARC oxide

This 900°C process uses a 10-minute deposition, a l-minute nitrogen soak, and a 3-hour oxidation. During the long oxidation, the junction is driven deeper, and a layer of silicon dioxide is grown at the silicon surface, increasing the total oxide thickness to the 110 nm necessary for a rudimentary antireflection coating. When the silicon surface is randomly textured /4/, this oxide gives a net reflectance of only about 2%. Fig. l shows the profile of this one-step emitter diffusion, measured at Sandia using SIMS.

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Fig. 900°C one-step phosphorus diffusion profile. We discovered that this baseline process is sensitive to exposure of the silicon surface to aluminum during the temperature rampup. If the wafers are loaded in the furnace boat such that the exposed surface to be doped with phosphorus is facing a surface coated with aluminiun, the one-step process reverts to normal behavior, and the sheet resistance obtained drops by an order of magnitude. This failure of the one-step diffusion process occurs even if the aluminum surface is covered with a layer of deposited oxide several hundred nanometers thick. We successfullyavoid this problem by being careful to flip the wafers during loading so that the silicon surfaces to be doped always face each other. We observed that the oxide produced by the one-step process is not uniform throughout its thickness; rather, it is composed of a dense thermal oxide at the silicon interface that provides excellent passivation, covered by a phosphorus-rich layer that etches quite rapidly in hydrofluoric-acid solutions. Fig. 2 illustrates the etching behavior of the oxide in a mixture of IO parts deionized water to one part concentrated hydrofluoric acid, at room temperature. In this example, the dry thermal oxide is about 35 nm thick, and the overlying phosphorus glass is about 65 m thick, corresponding well with the deposited phosphorus-glassthickness shown in Fig. A-6.

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Fig. 2 Etching one-step diffusion oxide in dilute HF We found that the phosphorus glass can be removed without adversely affecting the surface passivation of the layer (as measured using microwave photoconductance decay to determine the emitter saturation current density 151). In fact, the oxide can be etched back to as little as 5 nm before deterioration of the surface passivation is observed. Thus, it is possible to retain the surface passivation from this step while thinning the oxide to make it compatible with deposited antireflection coatings. 5. Cell Fabrication Results Our baseline cell fabrication process combines the one-step

phosphorus diffusion with random surface texturing, an aluminum-alloy back-surface contact, and evaporated gridlines. Random pyramidal texture is obtained on monocrystalline wafers using dilute potassium hydroxide and isopropyl alcohol at a temperature of 70°C. The aluminum alloy is normally performed at 800°C before the emitter diffusion, although we have made cells with the alloy after the diffusion and even by performing the alloy during the phosphorus diffusion. Gridlines up to 6 pm thick are formed using image-reversed photolithographic liftoff of evaporated Ti/Pd/Ag. Aluminum is used to contact the back surface, with TiiPdlAg added when needed for solderability. Eight or more separate cells are formed on each wafer to obtain data on spatial uniformity. Four-cm2 cells are used for onesun testing, and 1-cm2 cells are used for concentrated light. The cells are isolated from each other using a field oxide that is deposited using atmospheric-pressure chemical-vapor deposition at 400°C. This field oxide also serves as a pattern mask for the texture-etch solution. To reduce reflectance below that obtained using the 110-nm oxide resulting from the one-step diffusion process, antireflection coatings are applied after etching the diffusion oxide to a thickness near 10 nm. We have deposited Ti02 by electron-beam evaporation and Si02 by atmospheric-pressure chemical vapor deposition. On planar-surface cells, we have demonstrated a duallayer coating of Ti02 and Si02 using sol-gel solutions applied with a spinner. The sol-gel coating is particularly interesting because the deposited layers, prior to their densification at 4OO0C, can be patterned using buffered oxide etchant. We have processed more than 50 batches of solar cells using this baseline one-step diffusion process. We routinely obtain cell efficiencies over 19% using this process on 0.4-Qcm float-zone wafers and over 18% on 10-Rcm semiconductor-grade Czochralski wafers. Run-to-run variation in sheet resistance for the 900°C process has been within *lo%, excluding occasional shifts in the baseline caused by equipment alteration. The excellent surface passivation of cells produced using this process

is evidenced by internal quantum efficiencies at 400-nm wavelength that are routinely over 95%. The one-step diffusion process is ideally suited to solar-grade materials that cannot tolerate multiple high-temperature excursions. Using this process, we demonstrated a record one-sun cell efficiency of 17.6% and concentrator cell efficiency of 20.0% on solar-grade Czochralski silicon from Siemens Solar Industries /6/. We frequently obtain efficiencies over 15% using multicrystalline silicon material from Crystal Systems. Further improvement is expected as we gain a better understanding of impurity gettering in these materials. 6. Summary We developed a POCl3 one-step furnace process that produces a nearly ideal phosphorus emitter diffusion profile, grows a highquality passivating surface oxide, and can leave the cell with an antireflection coating that is adequate for process development experiments. We discovered that if the furnace ambient is switched to pure oxygen during the phosphorus diffusion process, further injection of phosphorus into the wafer is inhibited. Consequently, it is possible to deposit the phosphorus glass, allow it to diffuse into the silicon using a nitrogen ambient, then switch to oxygen to drive the junction deeper without reducing the sheet resistance. By suitable selection of process parameters, the oxide on the surface can be tuned to the antireflection thickness of 110 nm. Our one-step process produces a two-layer oxide stack, with a high-quality thermal oxide at the silicon interface, covered by a glass layer with high phosphorus content. The phosphorus glass etches off rapidly in solutions involving hydrofluoric acid, leaving behind the hard thermal oxide for surface passivation. The one-step process is ideally suited to solar-grade materials that cannot tolerate multiple high-temperature excursions. We are now actively involved in optimizing this process for a variety of multicrystalline silicon materials produced by manufacturers throughout the United States.

Acknowledgments The exceptionally thick metal evaporations used in our cell fabrication are performed by Jeff Tingley. Most of our chemical processing is performed by Beverly Silva. Herb Tardy developed our sol-gel and electron-beam antireflection coatings. REFERENCES [l] S. Wenham, "Buried-contact Silicon Solar Cells," Progress in Photovoltaics, 1 (l), 1993, pp. 3-10 [2] J. Coppye, M. Bhannam, J. Szlufcik, M.E. Elgamel, J. Nijs, Le Quang Nam, and M. Rodot, "High Efficiency Polycrystalline Silicon Solar Cells with Conventional and Selective Emitters", 22nd IEEE PVSpecialists ConJ.',1991, pp. 1020-1025. [3] J.M. Gee, W.K. Schubert, and P.A. Basore, "Emitter Wrap Through Solar Cell," 23rd IEEE PVSpecialists Con$, 1993. [4] D.L. King and M.E. Buck, "Experimental Optimization of an Anisotropic Etching Process for Random Texturization of Silicon Solar Cells, 22nd IEEE PVSpecialists Con$, 1991, pp. 303-308. [SI P.A. Basore and B.R. Hansen, "Microwave-Detected Photoconductance Decay," 21st IEEE PVSpecialists Con$, 1990, pp. 374-379. [6] D.S. Ruby, P.A. Basore, M.E. Buck, J.M. Gee, W.K. Schubert, and H.L. Tardy, "Simplified Processing for 23%Efficient Silicon Concentrator Solar Cells," 23rd IEEE PV Specialists ConJ, 1993.

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