Solid-State Electronics 48 (2004) 1511–1517 www.elsevier.com/locate/sse
Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis P. Dimitrakis a,*, E. Kapetanakis a, D. Tsoukalas a, D. Skarlatos a, C. Bonafos b, G. Ben Asssayag b, A. Claverie b, M. Perego c, M. Fanciulli c, V. Soncini d, R. Sotgiu d, A. Agarwal e, M. Ameen e, C. Sohl e, P. Normand a a
IMEL, NCSR ‘‘Demokritos’’, Institute of Microelectronics, 15310 Aghia Paraskevi, Greece b CNRS/CEMES, 29 rue Jeanne Marvig, 31055 Toulouse, France c Laboratorio MDM––INFM, Via C. Olivetti 2, 20041 Agrate Brianza (MI), Italy d ST Central R&D Agrate, Via Olivetti 2, 20041 Agrate Brianza, Italy e Axcelis Technologies, Inc., 55 Cherry Hill Drive, Beverly MA 01915, USA Available online 27 April 2004
The review of this paper was arranged by Dr. B. De Salvo and Dr. S. Lombardo
Abstract Si-nanocrystal memory devices aiming at low-voltage non-volatile memory applications are explored. The devices consist of a single metal-oxide-semiconductor field-effect-transistor with silicon nanocrystals fabricated through ultralow-energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing. Process issues like boron contamination and parasitic currents that affect the threshold voltage and transfer characteristics of the intended devices are discussed in terms of device structure, process parameter and device simulation. It is shown that these issues can be overcome under appropriate process modifications. Threshold shift of about 2 V are obtained for a 10 ms +9 V/)9 V pulse regime where both electron and hole trapping occur. Neither degradation, nor drift in memory window is detected after 1.5 · 106 10 ms +9 V/)9 V cycles. Charge retention measurements reveal that the de-trapping mechanism of stored holes is faster than that of trapped electrons and independent on the temperature. Memory operation with reduced hole trapping, herein demonstrated for a 10 ms +9 V/)7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 C, should be preferred for long non-volatile retention of years. 2004 Elsevier Ltd. All rights reserved. Keywords: Nanocrystals; Non-volatile memory; Ion implantation; Ion-beam synthesis; Nanocrystal memory
1. Introduction To overcome the limitations of current memory technologies and successfully respond to new market opportunities several novel fabrication routes and architectures are being actively investigated. Introduced in the early 1990s [1] as an alternative to conventional floating-gate non-volatile memories (e.g. FG NVM) for
*
Corresponding author. Tel.: +30-210-650-3271; fax: +30210-651-1723. E-mail address:
[email protected] (P. Dimitrakis).
fast, low-cost, ultra-dense data storage and low-power operation, nanocrystal based memories have attracted a great deal of interest and today many research groups are actively involved in this area. One of the main advantages of nanocrystal memories over conventional FG NVM devices lies in the use of mutually isolated charge storage nodes instead of a continuous polysilicon layer. Such a ‘discontinuous’ floating gate reduces charge loss through defect paths in the underlying tunnel oxide, thus allowing a scaling-down of the tunnel oxide. Moreover, compare to more mature technologies like SONOS that makes use of discrete traps distributed in a nitride layer, quantum confinement and Coulomb
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.03.016
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blockade (CB) effects can be exploited in nanocrystal floating-gate technology to improve the memory operation. Advantages and weaknesses of nanocrystal memories are discussed in [2]. The performance and the success of nanocrystal memories strongly depend on the following factors: (a) capacity to generate uniform, reproducible and tunable structures by a simple and flexible technique compatible with existing CMOS processes, (b) suitability of the technology route to generate nanocrystals at a desired location inside the gate oxide with integral injection and control oxides and defect-free SiO2 /Si interface, (c) the structural characteristics of the islands (such as size, shape and density) that influence the potential energy of trapped electrons, the Coulomb blockade energy, the channel screening efficiency and the electrical isolation of stored charges. As the optimum mean size of the nanocrystals is below the current lithography resolution, an attractive approach to fabricate nanocrystals is through a self-assembling process. Among the different processing routes explored during the last few years, the ion-beam synthesis (IBS) technique has received substantial attention because of its flexibility and its manufacturing advantages. The potential of IBS for nanocrystal memory applications has been recently enhanced through the synthesis in the ultra-low-energy (ULE) regime (typically 1 keV) of 2-D arrays of silicon nanocrystals in thin SiO2 films [3–6]. In terms of structural possibilities, a combination of ULE-IBS conditions and oxide thickness allows for the formation of Si nanocrystals at a location from the SiO2 /Si interface that can be tailored (see Fig. 1) for DRAM-like or EEPROM-like memory applications [1,6,7]. Although from a device fabrication point of view, ULE-IBS appears as a quite simpler technique compared to the traditional multi-step deposition ones, there are many technological issues that remain to be solved before establishing a fabrication process leading to reliable and reproducible (from a fabrication site to another) memory structures. We have recently tackled some of these issues (e.g. charge neutralization and energy contamination of implanted species, post-implantation cleaning process [8,9]) as well as alternative processing options (e.g. annealing in N2 /O2 for implantation damage recovery [10]) for high-dose ULE silicon implants. An important issue introduced in [8] and herein discussed relates to boron contamination. Introduction of boron during Si implantation may become a significant concern especially when using lowenergy implanters dedicated to boron implantation for ultra-shallow junction formation. Boron contamination of the channel region of transistors can significantly shift the threshold voltage, thus altering the intended device properties. The overcoming of many concerns pertaining to the aforementioned issues allow for the fabrication of competitive and reliable memory struc-
Fig. 1. (a) Schematic of the fabricated memory transistor structure where the channel edge regions (CE) and channel central region (CCR) are assigned. The gate oxide thickness of implanted devices is about 14 nm and the final boron concentrations are 4.5 · 1017 cm3 and 2 · 1017 cm3 at the dW regime and 3 lm from the channel edge, respectively. (b) Typical transfer characteristics of enhancement-mode NMOSFET devices with 7 nm (R7D) and 9 nm (R9D) thick gate oxides and silicon-implanted enhancement- and depletedmode NMOSFETs. A theoretical subthreshold IDS –VGS curve of an E-NMOSFET with 14-nm gate oxide thickness (R14D) is also drawn to emphasize the effect of boron contamination.
tures, as it is herein demonstrated for the case of NC-FG MOSFETs aiming at low-voltage non-volatile memory applications.
2. Experimental 3-in. p-type (1 0 0)-oriented silicon wafers were employed. The fabrication process used a 2-lm technology and was similar to that of conventional enhancementmode nMOS self-aligned poly-Si gate transistors (hereafter referred as E-NMOSFETs) except for the additional steps related to the fabrication of Si nanocrystals. Formation of the device isolation oxide (the socalled field oxide) and channel stopper is carried-out through the use of a non-self-aligned field oxide technique consisting in: (a) thick sacrificial oxide growth, (b) oxide patterning, (c) boron implantation, (d) field oxide
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growth (0.6 lm) and patterning. This last step defines the transistor area (including source, drain and channel regions) of the devices. Since the width of the oxide pads formed in step (b) upon the transistor area is about 4 lm (2 · dW , see Fig. 1a), smaller than the channel width defined in step (d), channel stop doping exceeds laterally the field oxide edge (hereafter also referred as the channel edge) to a distance around of 2 lm (dW ). Taking into account this patterning parameter and the thermal budget of field oxide formation, SUPREM process simulations indicate a boron surface concentration of about 2.5 · 1017 cm3 at dW from the channel edge (CE, see Fig. 1a). Boron concentration at 1.5 lm from dW inside the active region is about 2 · 1016 cm3 . After field oxide formation, boron-channel implantation is performed at 40 keV to a dose of 4 · 1012 cm2 through a 25-nm thick sacrificial oxide. Following sacrificial oxide removal, a 7-nm thick gate oxide is thermally grown and fabrication of Si nanocrystals by ULE-IBS is performed. For this purpose, Si implantation was carried out at 1 keV (5:1 keV deceleration regime) to a dose of 2 · 1016 cm2 . Implantation was performed at room temperature in an Axcelis GSD-implanter making use of a plasma electron flood to ensure charge neutralization. Subsequently, the wafers were cleaned using a Piranha solution (SPM: H2 SO4 :H2 O2 , 1:1 for 15 min) that does not affect the integrity of the implanted oxides [8,9]. After rinsing in deionized water and drying, thermal annealing was performed at 950 C for 30 min in nitrogen diluted oxygen (1.5% O2 per volume). Then, a polysilicon layer was deposited and etched to form the gate electrode. Formation of the source and drain regions was achieved through ion implantation and annealing at 900 C for 20 min in N2 ambient. The fabrication process was completed with the deposition of a passivation oxide, contact patterning and wet etching, and metal deposition, patterning and etching. Finally, a sintering anneal in H2 / N2 forming gas was performed. Fabricated E-NMOSFETs have a channel width (W ) of 100 lm and channel lengths (L) ranging from 2 to 10 lm. Process simulations indicate a final channel boron concentration of about 2 · 1017 cm3 at 3 lm from the channel edge and 4.5 · 1017 cm3 in the dW region. From TEM measurements performed on test samples with 7-nm thick oxides implanted and annealed under the same conditions, the thickness of the injection and control oxides and nanocrystal band for the present devices are estimated to be 6.5, 5 and 2.5 nm, respectively. It should be here emphasized that as a result of implantation damage recovery during annealing in diluted oxygen, the control oxide exhibits better insulating properties than the injection oxide despite a smaller physical thickness [10]. Moreover, plan-view energyfiltered images shows that the surface density of the nanocrystals is about 1.7 · 1012 cm2 .
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3. Results and discussion The transfer characteristics ðIDS –VGS Þ of Si-implanted E-NMOSFETs are shown in Fig. 1b and compared with those of reference E-NMOSFETs with non-implanted 7- and 9-nm thick gate oxides (hereafter referred as R7D and R9D). Threshold voltages of 0.39, 0.48 and 1.36 V are detected for R7D, R9D and Si-implanted devices. The threshold voltage is herein defined at IDS ¼ ðW =LÞ 10 nA. Considering the expected threshold voltage (0.77 V) of non-implanted E-NMOSFETs with 14-nm thick gate oxide, it appears that the threshold voltage of the Si-implanted E-NMOSFET is increased of about 0.6 V. Substrate doping evaluation from C–V measurements performed on chip-integrated capacitors indicates a doping density of about 1.8 · 1017 cm3 for the reference devices and 4 · 1017 cm3 for the Siimplanted devices. It should be noted that channel doping of the reference devices agrees with the simulation results (2 · 1017 cm3 ) given in Section 2. Although the contribution of positive charge formation due to the presence of excess silicon in close proximity to the channel cannot be totally excluded [11], it is believed that the threshold voltage shift detected for Si-implanted E-NMOSFETs is mainly due to an increase in doping density resulting from boron contamination introduced during Si implantation as discussed in Ref. [8]. In an effort to compensate this extra boron-channel doping, an additional step of arsenic implantation (5 · 1012 cm2 /130 keV) was performed after boron-channel implantation on NMOSFETs located on the same wafer as the previous E-NMOSFETs. The transfer characteristics of the resulting ‘depletion’-mode n-channel NMOSFETs (hereafter referred as D-NMOSFETs) are shown in Fig. 1b. These devices exhibit a mean threshold voltage of about 0 V. The transistor’s static parameters were extracted by the analysis of the transfer characteristics for low VDS (100 mV) and for VGS values in a range where no hysteresis occurs in the drain current. The subthreshold swing S has been calculated as equal to 115 mV/dec for both E- and D-NMOSFETs while for R7D and R9D devices it is about 84 mV/dec. C–V measurements performed on test MOS capacitors reveal that the interface states density Dit at midgap is below 1011 cm2 eV1 . These values are quite acceptable and suggest that the ULE-IBS process does not affect drastically the quality of the interface. The action of symmetric positive and negative gate voltage pulses on the transfer characteristics of E- and D-NMOSFETs is shown in Fig. 2. The pulse amplitude was fixed at +8 V or )8 V and the pulse duration varied from 0.5 to 500 ms. Application of negative and positive pulses results in a translation of the IDS –VGS characteristics to more negative and positive values, respectively, indicative of positive (holes) and negative (electron) charges trapped into the oxide. For commodity, the
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Fig. 2. Transfer characteristics of (a) D-NMOSFETs and (b) E-NMOSFETs after application of ±8 V voltage pulses of various durations. The onset of parasitic transistor that appears for the ‘write’ mode of E-NMOSFETs is activated after programming times higher than 1 ms.
device states following the application of positive and negative pulses are herein referred as ‘write’ and ‘erase’ states, respectively. While no variation in subthreshold slope is detected for D-NMOSFETs in the ‘write’ and ‘erase’ states, a hump in the subthreshold IDS –VGS characteristics of E-NMOSFETs occurs after application of positive pulses of duration larger than 0.5 ms. This current hump is indicative of parasitic transistors (FETp) that operate in parallel to the intrinsic transistor (FETi) as reported by Ohzone et al. [12] in the case of E-NMOSFETs using Si-implanted 50-nm thick gate oxides. In this case, device isolation is achieved through a LOCOS process. Ohzone et al. suggest that the thick gate oxide near the channel edge (bird’s beak region) and the lateral diffusion of channel-stopper boron atoms result in the formation of parasitic transistors close to the channel edges. These parasitic transistors exhibit a higher threshold voltage than that of the intrinsic tran-
sistor located in the channel region with uniform boron doping and uniform gate oxide thickness. In the case of the E-NMOSFETs herein reported it is clear that boron concentration is higher near the channel edges (see Section 2), thus resulting to higher threshold voltages in these areas compared to the central region of the channel. Calculations of channel doping as a function of the threshold voltage indicate that channel boron concentration in the FETi (Vth ¼ 1:36 V) and FETp (Vth 1:77 V) regions are about 5 · 1017 and 7.3 · 1017 cm3 , respectively. The threshold voltage of parasitic transistors was extracted from the IDS –VGS curve on Fig. 2 obtained after application of 1 ms +8 V gate voltage pulse. These results that reveal a boron concentration in excess of 2.3 · 1017 cm3 in the channel edge region are in accordance with doping evaluation previously described where a boron concentration of 2.5 · 1017 cm3 was estimated for the dW region. It should be also emphasized that the small but effective programming action observed for the FETp indicates that charge storage occurs in the parasitic regions, probably near the channel edge, where the injection oxide is thicker than that of the FETi. Furthermore, in the case of D-NMOSFETs, process simulations taking into account boron contamination reveal that the uniform doped channel region is arsenic rich while the channel edge remains highly boron doped. In this case, the difference in threshold voltage between the FETi and FETp is too large for detecting any action of the latter before reaching programming saturation of FETi. It is also pointed-out that the parasitic transistors are not active when the E-NMOSFETs operate in the ‘erase’ state due to the lower threshold voltage of FETi compared with that of FETp. To disregard the effect of parasitic regions in the case of E-NMOSFETs, the memory window of E-NMOSFETs as a function of pulse duration shown in Fig. 2 has been evaluated at IDS ¼ 100 nA W =L and compared with this of DNMOSFETs. Results are presented in Fig. 3. Similar ‘write’/‘erase’ characteristics are detected for both types of devices, indicative of an uniform Si-nanocrystal surface density above the channel. The dependence of the threshold voltage shift of D-NMOSFETs on pulse amplitude and duration is shown in Fig. 4. In the case of positive pulses, threshold voltage saturation occurs at +8, +9 and +10 V for pulse widths of 100, 10 and 1 ms, respectively. The saturation regime is reached and remains constant for +8 and +9 V and pulse durations higher than 10 ms. Disregarding the possibility of charge trapping into structural defects located through the injection oxide and assuming that only one electron can be stored into a nanocrystal, the nanocrystals surface density is estimated [6] to be on the order of 1012 cm2 . In the case of negative pulses saturation is observed at higher applied voltage pulses for a given pulse duration. Moreover, the memory window
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Fig. 3. Programming windows for both D- and E-NMOSFETs after application of ±8 V voltage pulses of various durations. Threshold voltage of the enhancement-mode transistor was extracted at IDS ¼ 5 lA (far away from the FETp region).
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slightly decreases. Taking into account the direction of the applied electric field during the ‘write’ pulse, charge loss could happen only through the control oxide. The possibility of hole-injection from the n-type polysilicon gate to the nanocrystals through the control oxide is very low due to the high-energy barriers. In addition, the annealing process reduces the presence of traps in the control oxide that might enhance the conduction of holes. The application of high negative voltages (‘erasing’ pulses) results to an electric field into the gate insulator that favors the escape of trapped holes to the polysilicon gate. In this case, the electron injection from the gate electrode through the control oxide cannot be neglected. Two important specifications for non-volatile memories relate to the ability to endure repeated ‘write’/ ‘erase’ cycles and the ability to retain data over long periods of time. Endurance of the devices was tested on D-NMOSFETs through a 10 ms +9 V/)9 V ‘write’/ ‘erase’ pulse regime. Neither degradation, nor drift in memory window or change in subthreshold slope was detected after 1.5 · 106 ‘write’/ ‘erase’ cycles (see Fig. 5). The ability to withstand such a number of ‘write’/ ‘erase’ cycles is attractive for EEPROM-like applications. It should be remembered that in present EEPROM technologies, the endurance is typically limited to about 105 – 106 ‘write’/ ‘erase’ cycles due to the degradation of the tunnel oxide induced by hot electron injection and/or Fowler–Nordheim tunneling. After endurance testing, the devices were programmed to the ‘write’ or ‘erase’ state and data retention was investigated at temperatures ranging from 25 (room temperature) to 150 C. Except for room-temperature experiments, the samples were heated on a hot-chuck in air for several time periods. Between two sequential time periods the samples were cooled down to room
Fig. 4. Typical ‘write’ and ‘erase’ characteristics of D-NMOSFETs for pulse durations ranging from 10 to 500 ms. Saturation occurs at +8, +9 and +10 V for pulse widths of 100, 10 and 1 ms, respectively.
attainable in the negative saturation regime is larger than that obtained with positive voltage pulses. Action of ‘erase’ pulses includes both trapped-electron extraction and effective injection of holes and trapping. A possible explanation for the latter effect might be the storage of holes into trapping sites dispersed through the tunnel oxide [11,13]. In this case and assuming that electron storage occurs mainly in the nanocrystals, a faster charge loss rate is expected in the ‘erase’ state compared to the ‘write’ state and would be temperature dependent. This will be further discussed in the remaining part of this paper. Moreover, for programming/erasing voltages higher than those required for reaching the saturation regime, the memory window
Fig. 5. Endurance characteristics of D-NMOSFETs tested through 1.5 · 106 10 ms +9 V/)9 V w/e cycles and subsequent 1 · 106 10 ms +9 V/)7 V w/e cycles. Neither degradation, nor drift in memory window was detected in both cases.
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temperature and threshold voltage measurements were carried-out. Results are presented in Fig. 6. While a slight decreasing in threshold voltage is observed for the ‘write’ state related to electron storage, the ‘erase’ state induced by holes injection into the oxide presents a significant decrease. Moreover, it appears that the decay rates of the hole-related memory windows are similar (0.165 V/dec) for all temperatures examined so far. This temperature independent charge loss process indicates that the hole-trapping sites are lying in direct tunneling distance from the Si/SiO2 interface and are not related to oxide deep traps whose emission rate is an explicit function of temperature: / T 2 expðEA =kT Þ [14,15], where EA is the activation energy (i.e. the position in the SiO2 energy band gap) of the trapping site. On the other hand, memory window decay rates related to the ‘write’ state are strongly temperature dependent ranging from 0.033 V/dec at 25 C up to 0.101 V/dec at 150 C. Although long time extrapolation gives attractive results, for example a 10-year memory window of about 0.4 V at 85 C, more experimental data are required for accurate calculations and before drawing safe conclusions on the decay rates and charge loss process of the ‘write’ state. This point is under investigation through experiments performed at higher temperatures and larger heating times. Furthermore, extrapolated values for the ‘erase’ state indicate that the threshold voltage becomes equal to that of the unstressed device for times smaller than 10 years (1.1 · 108 s for 85 C down to 5.3 · 106 s for 150 C), except in the case of room-temperature operation. Since the hole-injection ‘erasing’ part of the memory window presents limited data retention characteristics, the case of limiting the ‘erasing’ function to an effective removal of charge stored during the programming of the ‘write’
Fig. 7. Charge retention measurements at 150 C of DNMOSFETs previously stressed with: 1.5 · 106 10 ms +9 V/)9 V w/e cycles (case A), case A plus 106 10 ms +9 V/)7 V w/e cycles (case B), 106 10 ms +9 V/)7 V w/e cycles (case C).
state has been examined. Endurance tests were first performed on the previously 1.5 · 106 10 ms +9 V/)9 V stressed devices using a 10 ms +9 V/)7 V ‘write’/’erase’ cycle. As depicted in Fig. 5, although no saturation conditions were used for the ‘erase’ state no drift in memory window was detected after 106 ‘write’/’erase’ cycles. Afterwards, data retention measurements at 150 C were carried-out on these devices as well as on DNMOSFETs previously stressed only with 106 10 ms +9 V/)7 V cycles. Results are shown in Fig. 7. The threshold voltage for the ‘erase’ state slowly decreases with time and exhibits a trend for stabilization close to the threshold voltage of unstressed devices. Although similar decay rates for the ‘write’ mode are extracted for all devices it is expected that devices operating under a 10 ms +9 V/)7 V regime will exhibit higher withstanding and retention times after ‘write’/’erase’ cycles much larger than 1 · 106 . Considering the above, it is suggested that programming conditions with limited hole-injection should be preferred for long non-volatile retention of years. 4. Conclusions
Fig. 6. Data retention characteristics of D-NMOSFETs at room temperature (RT), 85, 115 and 150 C for 10 ms +9 V/)9 V programming conditions. The tested devices were previously stressed with 1.5 · 106 10 ms +9 V/)9 V w/e cycles.
Si-nanocrystals single-NMOSFET based memory devices were fabricated through ultra-low-energy (1 keV) Si implantation of a 7-nm thick gate oxide and subsequent thermal annealing. Device electrical behavior is discussed in terms of process parameter, device structure and simulation. Emphasis is placed on boron contamination that occurs during Si implantation and induces a substantial threshold voltage shift of the transistors. Also, parasitic currents that lead to a current hump in the transfer characteristics of enhancement-mode NMOS-
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FETs under ‘write’ mode operation and significantly affect the memory performance of the devices are discussed in terms of device geometry and channel doping. For the 2 lm device technology herein reported, it is shown that both boron contamination and parasitic current issues can be overcome through an additional arsenic channel implant step. Memory windows around of 2 V at voltage pulses as low as 9 V and pulse durations on the order of 10 ms are obtained in the case of programming conditions involving electron and hole trapping. Endurance testing shows that the devices can support more than 1 · 106 10 ms +9 V/)9 V cycles. Charge retention measurements at room temperature up to 150 C reveal that the escape process of trapped holes is fast and temperature independent while electron de-trapping is much slower and fulfills 10-year data retention criterion. Memory operation with reduced hole trapping, such herein demonstrated for a 10 ms +9 V/)7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 C, should be preferred for long non-volatile retention of years. Although further investigations are necessary to give a safe explanation of the observed memory behavior, it is pointed-out that the programming, endurance and retention time characteristics obtained throughout the measurements performed so far suggest that the devices reported herein are promising for low-voltage EEPROMs applications.
Acknowledgements This work was a part of the NEON project and was funded by the EC as GROWTH GRD1-2000-25619.
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References [1] Tiwari S, Rana F, Hanafi H, Hartstein A, Crabbe EF. Appl Phys Lett 1996;68:1377. [2] Blauwe JD. IEEE Trans Nanotechnol 2002;1:72. [3] White MH, Adams DA, Bu J. IEEE Circ Dev 2000; 16:22. [4] Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, Finzi D. IEEE Electron Dev Lett 2000;21:543. [5] Kapetanakis E, Normand P, Beltsios K, Tsoukalas D. In: Nalwa HS, editor. Encyclopedia of nanoscience and nanotechnology. USA: American Scientific Publishers; 2003, to appear. [6] Tiwari S, Rana F, Chan K, Hanafi H, Chan W, Buchanan D. IEEE IEDM Tech Dig 1995:521. [7] Bonafos C, Carrada M, Cherkashin N, Coffin H, Chassaing D, Ben Assayag G, et al. J Appl Phys 2004. [8] Normand P, Kapetanakis E, Dimitrakis P, Skarlatos D, Beltsios K, Tsoukalas D, et al. Nucl Instrum Meth B 2004;216:228. [9] Normand P, Dimitrakis P, Kapetanakis E, Skarlatos D, Beltsios K, Tsoukalas, D, et al. Microelectron Eng, in press. [10] Normand P, Kapetanakis E, Dimitrakis P, Tsoukalas D, Beltsios K, Cherkashin N, et al. Appl Phys Lett 2003;83: 168. [11] Kalnitsky A, Boothroyd AR, Ellul JP, Poindexter EH, Caplan PJ. Solid State Electron 1990;33:523. [12] Ohzone T, Michii A, Hori T. Solid State Electron 1995;38: 1165. [13] Ohzone T, Matsuda T, Hori T. IEEE Trans Electron Dev 1996;43:1374. [14] Kwon YH, Park CJ, Lee WC, Fu DJ, Shon Y, Kang TW, et al. Appl Phys Lett 2002;80:2502. [15] De Salvo B, Ghibaudo G, Pananakakis G, Reimbold G, Mondond F, Guillaumot B, et al. IEEE Trans Electron Dev 1999;49:1518.
