¨ 63 (2009) 871 -- 876 Int. J. Electron. Commun. (AEU)
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Self-controlled 4-transistor low-power min–max current selector Jordi Madrenas∗ , Daniel Fernández, Jordi Cosp, Luis Martínez-Alvarado, Eduard Alarcón, Eva Vidal, Gerard Villar Electronic Engineering Department, Universitat Politècnica de Catalunya (UPC), Jordi Girona 1-3, 08034 Barcelona, Spain
A R T I C L E
I N F O
Article history: Received 23 April 2008 Accepted 5 July 2009
Keywords: Analog VLSI Current rectifier Min–max selector Neuromorphic engineering Similarity detection
A B S T R A C T
Four cross-coupled MOS transistors operating as switches implement a very compact, fast, low-power and precise minimum and maximum current selector. Local positive feedback allows the circuit to work without the need of any control inputs and ensures very high sensitivity. Experimental results confirm the simulations and the analyzed second-order effects. Applications include min–max current selection and precision differential rectification. An application example of the cell to build a similarity circuit is reported. © 2009 Elsevier GmbH. All rights reserved.
1. Introduction Minimum and maximum (min–max) analog VLSI current selectors are versatile building blocks used in several applications such as nonlinear function synthesis (e.g. fuzzy logic and artificial neural models), neuromorphic systems and full-wave precision rectification. Current-mode min–max functions can be obtained from winnertake-all (WTA) circuits [1–4]. In particular, the initial proposal in [1], due to its simplicity and scalability, has been the starting point for many min–max circuits in fuzzy logic implementations, such as [5,6] and subsequent modifications [7,8]. Other min–max circuits [9–12] and rectifiers [13–18] with complex topologies allow to implement two-input min–max current selection but the area overhead of those proposals would be high for a compact and simple integration, especially in applications that require a massively parallel implementation of this function, such as image focal-plane image processing and other neuromorphic parallel processing systems. In this paper, a very compact circuit based on four cross-coupled MOS transistors that by construction do not require external control elements is introduced. The circuit accurately selects the minimum and maximum of two input currents. Because of its simplicity, the proposed circuit outperforms other existing two-input currentselection topologies reported up to now. In the next section, the current switch is introduced and analyzed. The circuit design and simulations are discussed in Section 3 and the circuit second-order
∗ Corresponding author. Tel.: +34 93 401 67 47; fax: +34 93 401 67 56. E-mail address:
[email protected] (J. Madrenas). 1434-8411/$ - see front matter © 2009 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2009.07.002
behavior is analyzed in Section 4. Experimental results of the measured cell are disclosed in Section 5, while in Section 6 the current selector circuit is applied to perform a selective similarity function to finally conclude in Section 7. 2. The basic circuit The circuit principle is shown in Fig. 1a. Two cross-coupled switch pairs detect at any time the minimum and the maximum of two input currents, I1 and I2 , directing them to IMIN and IMAX output lines, respectively. The proposed circuit is shown in Fig. 1b. It simply consists of the four switch transistors whose gates are connected to the input nodes. Thus, the switches are self-controlled by detecting voltage at their inputs, without any extra circuitry required. All transistor sizes are identical. For the analysis, the circuit can be interpreted as composed of two current mirrors with cross-coupled input and output nodes. Mirror M1A − M2B , controlled by V1 , implements the parallel switches and mirror M2A − M1B , controlled by V2 , the crossed ones. 2.1. Ideal analysis For the sake of simplicity, let us set the output voltage VREF = 0 V. Thus, nodes V1 and V2 completely determine the transistors' operating conditions. Assuming saturated transistors, with no Early (or channel-length modulation) effect and ideal current mirroring, and applying the Kirchhoff current law, the only compatible solution for the circuit is I1 = ID1A + ID1B = ID1A + ID2A
(1a)
I2 = ID2A + ID2B = ID2A + ID1A = I1
(1b)
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2.2. First-order large-signal analysis
I2
In real devices, a small enough input current difference does not turn off the loser mirror. If the Early effect is taken into account to obtain the circuit DC input–output characteristic around the equilibrium point, a first-order small-signal analysis leads to the same condition as Eq. (1), i.e., any I produces the loser mirror to turn off, because the MOS output resistance r0 in this model is constant. Thus, large-signal equations have to be used for this analysis to obtain a more realistic result. When applying opposite differential currents with I0 commonmode input current as shown in (2), V1 and V2 suffer an opposite variation until the Early effect compensates for the I current difference
I1
IMIN
IMAX
I1 = I0 +
I2
I1 = I0 −
I1
V2
V1
M1B
M2B
2
I 2
= ID1A + ID1B
(2a)
= ID2A + ID2B
(2b)
Considering the first-order MOS drain current model ID =
M2A
I
2
(VGS − VT ) (1 + VDS ) = IQ (1 + VDS )
(3)
where is the large-signal transconductance parameter, is the current-law exponent of the strong inversion MOS transistor ( = 2 for the long-channel model), and is the Early effect parameter. Substituting (3) into (2), and assuming reduced Early effect and small I, the following approximate V –I relation between the differential input current and the input voltage is obtained
M1A
I = I1 − I2 = (V1 − V2 )(IQ1 + IQ2 ) I0 (V1 − V2 ) IMIN
IMAX VREF
VREF
Fig. 1. (a) Circuit principle and (b) NMOS min–max current switch.
=
2 V r0
(4)
where r0 stands for the transistor output resistance with I0 /2 biasing. IMAX and IMIN are obtained as IMAX = ID1A + ID2A =
Thus, input currents have to be necessarily identical (I1 = I2 = I0 , where I0 is an arbitrary input current) to accomplish the equation constraints under those ideal conditions. At this equilibrium point, all transistors operate under the same electrical conditions and, because of circuit symmetry, ID1A = ID1B = ID2A = ID2B = I0 /2. Also, since V1 = V2 and VGS = VDS for all transistors, they all operate in the saturation region, validating the previous assumption. Finally, IMAX = IMIN = I0 . This implies that the circuit will only operate with all transistors saturated if I1 = I2 . Starting from the equilibrium point, let us assume that one of the inputs slightly increases, e.g., I1 = I0 + I. This rises V1 , because M1A has to drain now I0 /2 + I. Thus, M2B will in turn drain I0 /2 + I. This leaves M2A draining less current, I0 /2 − I, reducing V2 and the current drained by M1B also down to I0 /2 − I. This produces a new increase in the M1A current to I0 /2 + 2I, and this positive-feedback loop will continue until mirror transistors M1A −M2B drain I1 =I0 + I and I2 = I0 , respectively, while M2A − M1B turn off, regardless of the I value. Notice also that, with no Early effect, M2B has to operate in linear region to drain smaller current than M1A . Conversely, when I1 < I2 , M2A and M1B will drain I2 and I1 , respectively, while mirror M1A − M2B turns off. Summarizing, in a WTA-like competition, the mirror whose diode-connected transistor receives the largest current will finally drive both input currents and turn off the complementary mirror. In both cases, the larger input current is routed to the IMAX output and the smaller one, to IMIN .
2
[(V1 − VT ) (1 + V1 )
+ (V2 − VT ) (1 + V2 )] IMIN = ID1B + ID2B =
2
(5a)
[(V2 − VT ) (1 + V1 )
+ (V1 − VT ) (1 + V2 )]
(5b)
Subtracting expressions (5), and assuming small input voltage variations, IMAX − IMIN gm V 2
(6)
where gm is the transistor transconductance for I0 /2 biasing. Substituting (4) into (6), the differential output current is obtained as a function of the differential input current, IMAX − IMIN
gm r0 I2 A0 I2 = 2 I0 2 I0
(7)
where A0 = gm r0 is the transistor intrinsic gain. Since IMAX − IMIN is parabolic around the equilibrium point, because of symmetry considerations, IMAX and IMIN will also be parabolic around it. The first derivative of a parabolic expression is only 0 at its minimum. This result confirms that the circuit performs with the continuous derivative of a real system a good approximation of the desired peak shape.
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2.0
873
IMAX IMIN
1.8 1.6
Current (uA)
1.4 1.2 1 0.8 0.6 0.4 0.2 0.0
-2.0
-1.5
-1.0
-0.5 0 0.5 Differential current (uA)
1.0
1.5
2.0
Fig. 2. DC input–output characteristic. Inset: zoom of the crossing point.
(b) Closed-loop gain smaller than unity: AI = (1 + 1 )(1 + 2 ) < 1
3. Circuit design and simulation Fig. 2 shows simulated results of the circuit DC input–output current behavior for a differential-input I linear variation: I1 sweeps from 0 to 2 A while I2 spans from 2 A down to 0 A at the same time. As it can be observed, high-precision current rectification is obtained. A zoom inset shows the parabolic shape of IMAX and IMIN around the crossing point as calculated in (7). A 50-iteration Monte Carlo simulation indicates that for input currents with a crossing point at I0 = 1 A, the standard deviation of circuit offset is 64 nA, using the error parameters specified by the manufacturer. 4. Second-order effects Device non-idealities, mainly transistor mismatch, can produce several variations as compared to the ideal current selector. Different behaviors can be observed considering three possible error sources of the cross-coupled mirrors: different current gain and VT and VREF mismatch. 1. Closed-loop current gain different than unity. In (8), the current gain of mirrors M1A − M2B and M2A − M1B is expressed including error parameters 1 and 2 : ID2B = ID1A (1 + 1 )
(8a)
ID1B = ID2A (1 + 2 )
(8b)
If 1 0 and/or 2 0, the following cases and their effects can be considered: (a) Closed-loop gain higher or equal to unity: AI = (1 + 1 )(1 + 2 ) ⱖ 1 • Errors with different sign: sign(1 ) = −sign(2 ). An input offset current arises. • Errors with the same sign: sign(1 ) = sign(2 ). Switch hysteresis appears.
• Peak shape flattening: The corners of the peaks become rounded so that IMIN does not reach IMAX when input currents cross each other. 2. Threshold voltage (VT ) mismatch: input offset current. 3. VREF difference between output nodes: input offset current. Cases 1 and 2 produce similar offset effects because in both cases the effective transistors' VGS is modified. The non-ideal effects can be reduced by proper sizing and layout design techniques. Also, it is worth to mention that, in some cases, some degree of hysteresis or peak flattening could be of interest for a given application and can be intentionally applied by appropriate transistor sizing.
5. Experimental results A PMOS version of the min–max current selector has been designed and manufactured in a 0.35 m technology. All transistor sizes are W = 0.6 m, L = 0.6 m. Experimental measurements show good agreement with simulations. Fig. 3 shows a DC sweep of the input currents as in the simulation of Fig. 2. The center of the figure has been zoomed to highlight the error at the crossing point. As it can be seen, a 70 nA offset arises near that point. It is presumably produced by different current mirror gains, VT mismatch or VREF difference between output nodes. Besides offset, the predicted effects of peak flattening and hysteresis have also been experimentally observed in manufactured samples. These two effects may arise when current gain of mirrors is different than unity and they can be reduced by applying proper mismatch reduction techniques in the current mirrors, for instance increasing sizes and/or using common-centroid structures. Several dynamic measurements have also been carried out. As shown in Fig. 4, the current selector circuit correctly follows the input currents. The crossing point, the most critical, has been measured to have a settling time at least smaller than 10 s, since internal pad
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1.6 IMIN IMAX
1.5 1.4
MMAX
IMIN
1.3 Current (uA)
VDD
MMIN
1.2
IMAX VMIN
VMAX
1.1 1 0.9
M2A
0.8
M1B
M2B
M1A
0.7 0.6
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Differential current (uA)
V2
M2
M1
V1
Fig. 3. Measurement of the DC input–output characteristic. A zoom has been performed to enlarge the 70 nA current offset effect.
I0 VSS
1
Fig. 5. Selective similarity circuit. The min–max current selector circuit is embedded into the differential amplifier.
Current (uA)
0.9 IMIN IMAX
0.8
2.5
0.7 0.6
2
0.4 -0.8
-0.6
-0.4
-0.2 0 Time (us)
0.2
0.4
0.6
Fig. 4. Measurement of the transient input–output characteristic around the crossing point.
capacitances limit the measurement speed. The small overlapped oscillations are due to the off-chip I/V conversion measurement circuit dynamics. Simulations indicate that switching delay after inputs crossing is about 100 ns for a 4 A/ s linear variation of the input currents. 6. Circuit application: selective similarity cell An application example where a massive number of two-input min–max circuits is required is a neuromorphic system that performs gray-level image segmentation using coupled oscillators [19,20]. In this application, a function of the similarity of two neighbor pixels is required. This function has to deliver maximal response when two input currents are equal and progressively reduce its value as the inputs differ. In order to improve selectivity, a peak-shape response is targeted, so that it is maximal when the pixels' brightness is equal and progressively decreases as it becomes dissimilar [21]. In a focal-plane, parallel implementation of the algorithm on a CMOS photodetector array, two such functions are required per pixel. Thus, a compact implementation of min–max selectors becomes a key feature.
Current (uA)
0.5 1.5
IMIN IMAX
1
0.5
0 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 Differential Voltage (V) Fig. 6. Experimental DC input–output characteristic of the similarity circuit.
In Fig. 5, a PMOS version of the min–max current selector (in the center of the figure) is connected to the branches of a differential pair amplifier, loaded with diode-connected transistors. This circuit performs a peak-shaped function, as shown in the DC experimental measurement of Fig. 6. The output current of each branch is represented as a function of the applied differential input voltage sweep applied. The well-known differential pair V –I characteristic is rectified so that complementary peak-shaped functions are obtained. The functions, as desired in the application, saturate near the supply levels. In Fig. 7a, the optical microphotograph of the layout is shown. Since the number of metal layers does not allow appreciating the full layout, the designed layer figure is shown in Fig. 7b. The 4-transistor current selector is at the bottom of both figures, while the differential pair and current source are located at the left-hand side.
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crossing point error below 70 nA is obtained. Results show good DC and transient behavior. The circuit has been successfully used in a selective similarity function cell with satisfactory experimental results. Other possible signal processing applications of the proposed current selector are current-mode minimum–maximum detection and full-wave differential precision rectifying. Acknowledgments This work has been partially funded by Projects TEC200767144/MIC and TEC2008-06028. Daniel Fernández and Luis Martínez-Alvarado hold a research fellowship supported by the Catalan DURSI and the European Social Fund. The authors wish to acknowledge the valuable comments from the anonymous reviewers.
References
Fig. 7. Layout of the min–max current selector and selective similarity circuit: (a) microphotograph and (b) designed layout.
7. Conclusion A compact, self-biased and self-controlled 4-transistor minimum– maximum current detector has been presented. No extra control hardware is required due to the fact that the input nodes are used as control terminals. The small number of transistors and the absence of control circuit guarantee very low power consumption to perform the function. The positive feedback provides very precise switching at the crossing point, where all transistors operate in saturation, which guarantees fast switching. The circuit layout has been manufactured and experimentally measured. Even with reduced transistor size and low currents, a
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Jordi Madrenas received the M.Sc. and the Ph.D. degrees in Telecommunication Engineering from the Technical University of Catalunya (UPC), Barcelona, Spain, in 1986 and 1991, respectively. He is currently an Associate Professor at the Department of Electronic Engineering, UPC. Between 2000 and 2003 he was the Vice-Dean of Studies of the Telecommunication Engineering School of Barcelona, UPC. He has participated in several European and Spanish National Research Projects. Currently he coordinates a National Research Project on microsensor conditioning and bioinspired signal processing and he has co-authored more than 90 scientific papers in journals and conference proceedings and five book chapters. His research interests include analog, mixed-signal and digital VLSI and FPGA design, e-beam testing, bioinspired neural and neuromorphic systems implementation, focal-plane image segmentation, field-programmable mixed-signal arrays and MEMS conditioning. Daniel Fernández was born in Barcelona, Spain, in 1979. He received the M.Sc. degree in Telecommunication Engineering and the Master in Business Administration degree from the Technical University of Catalonia, UPC, in 2004 and 2009, respectively. In 2005 he joined the Advanced Hardware Architectures Group and he was awarded with a four-year FI Research Fellowship for pursuing a doctorate, receiving the Ph.D. degree from UPC, with honors, in 2008. Since then he is working as a Researcher at the Electronic Engineering Department, UPC, in the fields of CMOS surface micromachining, circuits and control architectures for MEMS electrostatic actuators, translinear circuits for analog signal processing and digital implementation of power converters.
Jordi Cosp received both the M.Sc. and the Ph.D. degrees (with honors) in Telecommunication Engineering from the Universitat Politecnica de Catalunya (UPC) in Barcelona, Spain, in 1995 and 2002 respectively. During the period 1997–2000 he held a FI Research Fellowship at the Department of Electronic Engineering, UPC. In 2000 he became an Assistant Professor at UPC. He has participated in several European and National Research Projects in the last years. His research interests include neuromorphic engineering, MEMS signal conditioning, analog and digital VLSI design, nonlinear oscillators and image processing implementation schemes. Luis Martínez-Alvarado was born in México, in 1976. He received the B.Sc. degree in Electronic Engineering from Mexicali Institute of Technology and the M.Sc. degree in Electronic Design from CINVESTAV Guadalajara, México, in 1999 and 2002 respectively. He is currently working in his Ph.D. degree at the Technical University of Catalonia in the Advanced Hardware Architecture Group. His main interest areas are reconfigurable mixed-signal systems, MEMS sensor conditioning and mixed-signal system high-level modeling.
Eduard Alarcón received the M.Sc. (national award) and the Ph.D. degrees in Electrical Engineering from the Technical University of Catalunya (UPC), Barcelona, Spain, in 1995 and 2000, respectively. Since 1995 he has been with the Department of Electronic Engineering at the Technical University of Catalunya, where he became an Associate Professor in 2000. From August 2003 to January 2004, he was a Visiting Professor at the CoPEC Center, University of Colorado at Boulder, USA. He has co-authored more than 130 international scientific publications, three book chapters and two patents, and has been involved in different national and US R&D projects. His current research interests include the areas of analog and mixed-signal integrated circuits, on-chip power management circuits, wireless energy transfer and nanonetworks. He was a recipient of the Myril B. Reed Best Paper Award at the 1998 IEEE Midwest Symposium on Circuits and Systems. He served as an Associate Editor of the IEEE Transactions on Circuits and Systems – II: Express Briefs (2006–2007) and currently serves as an Associate Editor of the Transactions on Circuits and Systems – I: Regular Papers (2006–2009).
Eva Vidal received her M.Sc. and Ph.D. degrees (both with honors) in Electrical and Electronics Engineering (Master in Telecommunications) from the Universitat Politècnica de Catalunya in Barcelona, Spain, in 1993 and 1998, respectively. During the period 1993–1994 she was an Assistant Professor at the Department of Electronics Engineering of the Universitat Rovira i Virgili of Tarragona. From 1994 to 1998 she was an Assistant Professor at the Department of Electronics Engineering of the Telecommunication Engineering School of Barcelona, where she became a full-time Associate Professor in December 1998. Her research focuses in the area of analog circuit design with emphasis in analog microelectronics and particular interest in current-mode design, automating tuning design, analog baseband circuits, wireless transceiver architectures and nonlinear analysis of oscillators. She has authored or co-authored about 50 scientific papers in journals and conference proceedings and was the invited co-editor of a special issue of the Analog Integrated Circuits and Signal Processing Journal devoted to current-mode circuit techniques.
Gerard Villar received his M.Sc. in the Technical University of Catalonia in 2001, and his Ph.D. in November 2007, at the same university. In April 2008 he became a Research Scientist at the Mixed-Signal Circuits and Systems Group, of the Research Division of NXP Semiconductors, where he has been working on integrated power management systems. His main research areas include mixed-signal and analog microelectronics design, as well as power management systems (including switched-mode power supplies).
