Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2010, Article ID 979120, 9 pages doi:10.1155/2010/979120
Research Article Modified Polar Sigma-Delta Transmitter for Multiradio Applications Martha Liliana Suarez Penaloza,1 V´aclav Valenta,1, 2 Genevi`eve Baudoin,1 Martine Villegas,1 and Roman Marˇsa´ lek2 1 Universit´ e
Paris-Est, ESYCOM, ESIEE Paris, 93160, Noisy-le-Grand, France of Radio Electronics, Brno University of Technology, 61200, Brno, Czech Republic
2 Department
Correspondence should be addressed to V´aclav Valenta,
[email protected] Received 7 June 2010; Revised 20 August 2010; Accepted 16 September 2010 Academic Editor: George Tombras Copyright © 2010 Martha Liliana Suarez Penaloza et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Radio transmitters capable of transforming variable envelope signals into constant envelope signals can be associated with highefficiency switched mode power amplifiers. One of the techniques providing this conversion is Polar Sigma-Delta (ΣΔ) architecture. This approach provides efficient solution for high-dynamic signals, and, moreover, it offers flexibility in a multiradio environment. The overall concept of the polar ΣΔ transmitter is presented here along with novel modifications and improvements. Namely, when recombining the envelope and the phase signals, it is suggested to replace the analog mixing by a digital mixing. The impact of a frequency synthesizer with a switched loop bandwidth and its imperfections on the overall polar ΣΔ architecture is investigated as well. The Mobile WiMAX standard has been chosen for validation due to very high requirements in terms of power dynamics and the variable channel bandwidth. Simulation results are presented in this paper, and advantages and drawbacks of this novel approach are pointed here as well.
1. Introduction Recent years have seen a considerable development of wireless communication systems such as cellular communications, Personal Area Networks (PANs), Local Area Networks (LANs), and Metropolitan Area Networks (MANs), and they keep evolving at a rapid pace. Coexistence of different wireless standards on the same device is necessary to satisfy all users who expect mobility, ubiquitous connection, and high data rates. At the same time, this coexistence should not penalize the size of the radio device nor reduce the battery life. Building separate transceivers for individual modes of operation is a straightforward task, and it provides the best performance for each mode, but on the other hand, it significantly penalizes the overall complexity, power consumption, and implementation costs. Therefore, a multiradio transceiver that combines low power and low costs by sharing reconfigurable components and that is capable of generating any arbitrary waveform becomes the ulti-
mate goal. This concept is known as a multi-radio transceiver. A multi-radio transmitter should be able to support the most diffused wireless communication standards in the radio band of 800 MHz to 6 GHz and be able to adapt its operating parameters to required specifications [1]. It has to cope with variable signal dynamics, which in turn requires high linearity and low-noise performance of the whole transmission chain. Moreover, a multi-radio transmitter has to support variety of different frequency bands and wide range of different channel bandwidths. Furthermore, a cognitive multi-radio is an evolution of the multi-radio concept that is capable of performing efficient environment spectrum scanning. It can adapt to conditions of the environment and user’s needs by choosing the most appropriate communication standard. The polar ΣΔ transmitter may be used for multi-radio applications when the RF elements of the architecture are designed for the most restrictive parameters of a given communication standard, as suggested in [1].
The overall architecture of the polar ΣΔ transmitter is given in Section 2. Suggested modifications are presented and analysed afterwards. Mobile WiMAX standard and related simulation parameters are introduced in Section 3. Section 4 is focused on a particular design of a frequency synthesizer and on the impact on the proposed polar ΣΔ transmitter. The digital mixing approach and simulation results are presented and summarized in Section 5.
To reach very high data throughputs, advanced spectrumefficient modulation techniques have been employed in modern wireless communication systems. Unlike modulation techniques used in 2G and preceding wireless systems, most of recent wideband modulation techniques such as the Orthogonal Frequency Division Multiplexing (OFDM) imply high Peak to Average Power Ratio (PAPR) and high degree of RF design complexity. The PAPR may reach up to 29 dB, which is the theoretical maximum in case of the mobile WiMAX standard. This in turn implies stringent linearity requirements on linear Power Amplifiers (PAs) that are typically used in homodyne and heterodyne radio transmitters. However, amplification of variable envelope signals by linear amplifiers results in a significant drop of power efficiency due to the large PAs backoff that is required for distortion-free amplification. A solution to this problem may be offered through linearization techniques [2] or through different signal decomposition techniques [3]. Different architectures based on the signal decomposition principle vary, and they can be classified depending on the way the variable envelope is coded and the way the envelope information is reintroduced to the constant-envelope phase signal (recombination or reconstruction of the variable envelope signal). Polar architectures decompose the high PAPR signal into two components: a constant envelope phase signal and a variable envelope signal. The complex envelope z(t) of a baseband-modulated signal (QPSK, m-QAM, OFDM, etc.) can be expressed as z(t) = zI (t) + jzQ (t).
(1)
The resulting envelope ρ and both phase signals cos(φ) and sin(φ) are separated, mathematically:
cos φ =
zI (t) , ρ(t)
2
,
(2)
zQ (t) . ρ(t)
(3)
sin φ =
ΣΔ (digital) cos (φ)
PLL sin φ
+
−
PA
Digital
Figure 1: Architecture of a polar ΣΔ transmitter with baseband recombination.
2. Polar ΣΔ Architectures for Multi-Radio Applications
ρ(t) = (zI (t))2 + zQ (t)
ρ
DAC
EURASIP Journal on Wireless Communications and Networking
DAC
2
The purpose of the decomposition is to amplify the constant envelope signal in a high-efficiency nonlinear switched mode RF PA (that offers theoretically 100% efficiency as the current and the voltage arises at different time intervals) and, moreover, to avoid AM/AM and AM/PM distortions [4, 5].
Specific classification of transmitters based on these principles is summarized in [1]. Particularly, two different approaches to the polar ΣΔ transmitter have been introduced in [6, 7]. Polar architecture proposed in [7] modulates the baseband envelope signal ρ by a 1-bit low-pass ΣΔ modulator (having a variable output ± a) and thereby transforms the envelope variant signal into a constant envelope signal. Components of the phase signal (cos(φ) and sin(φ)) have inherently constant envelope nature. The envelope and phase signals are then recombined and RF modulated in an IQ modulator or in a modulated Phase Locked Loop (PLL). Since the resulting recombined signal has a constant envelope, a high-efficiency switched mode amplifier can be used. Amplified signal is then filtered by a band-pass filter to restore the initial shape of the signal (Figure 1). Another approach proposed in [6] is depicted in Figure 2. This architecture has been optimized in [8] to overcome the noise convolution problem and to improve the in-band Signal to Noise Ratio (SNR) performance. Nevertheless, the proposed improvements use feedback loops, which in turn reduce the maximum bandwidth of the input signal (as the whole feedback systems acts as a low-pass filter). When comparing these two polar architectures, it is evident that in [7], the restoration of the envelope and the phase is carried out in the baseband, and hence, the synchronization becomes easier compared to the RF polar ΣΔ transmitter [6]. Delay mismatch between the envelope and phase signals is not as severe issue as in the classical Envelope Elimination and Restoration (EER) architecture [1]. However, one of the challenges of this architecture (as any polar architecture) comes out from the conversion from Cartesian to Polar coordinates. This conversion leads to bandwidth expansion and, therefore, to higher requirements on the sampling rate. In the polar architecture proposed in [7], the output signal of the ΣΔ modulator as well as the zI (t) and the zQ (t) signals (ρ cos(φ) and ρ sin(φ)) are digital. Therefore, as shown in Figure 1, two Digital-to-Analog Converters (DACs) need to be employed before the upconversion stage. The sampling frequency of DACs is chosen according to the ΣΔ frequency and it has to be high enough to avoid undesired overlapping of the ΣΔ quantization noise [9]. Communication standards in our multi-radio concept require high ΣΔ frequencies and therefore significant sampling frequency for DACs.
EURASIP Journal on Wireless Communications and Networking Envelope detector
ΣΔ
ρ(n) DC supply
τ
e jφ(t)
RF input
˜ A(t)
Digital ΣΔ RF filter
RF output
PA
x(t) φ(n)
PA
ADPLL
Digital
Figure 2: Architecture of a polar ΣΔ transmitter with RF recombination [6].
ρ
3
Digital ΣΔ
φ(t) Digital
DAC
x(t)
φ (t)
PLL
PA
cos (wc t + φ (t))
Figure 3: Architecture of the modified polar ΣΔ transmitter.
From this point onward, the polar ΣΔ architecture notation will refer to the architecture proposed in [7]. 2.1. Modified Polar ΣΔ Architecture. Instead of decomposing the complex envelope signal into ρ(t), sin(φ), and cos(φ) as suggested in [7], the modified architecture depicted in Figure 3 separates the envelope and phase signals into ρ(t) and φ(t) and processes them independently. Digital phase signal is converted to analog and then modulated to the carrier frequency f c . Finally, the constant envelope signal and the phase signal are recombined. The advantage compared to [7] is that only one DAC is required. Furthermore, DAC frequency requirements can be relaxed. Independent processing of ρ(t) and φ(t) is also suggested in [6]; however, this approach does not consider issues related to DAC conversion and issues regarding the appropriate choice of DAC and ΣΔ sampling frequencies. The latter issues are analyzed hereafter in detail. The polar ΣΔ architecture proposed in [7] upconverts the baseband signal to the carrier frequency through an analog IQ modulator. Similarly, the modified ΣΔ architecture we propose here employs an analog multiplier to recombine the envelope and phase signals. The next section suggests generating a digital carrier and replacing the analog mixer by a digital mixer. 2.2. Polar ΣΔ Architecture with Digital Mixing. Figure 4 presents a scheme of the digital mixing polar ΣΔ architecture. In this case, an All Digital PLL (ADPLL) generates the carrier frequency. The digital mixing can be assured by an AND gate as suggested in [10]. Compared to the architectures proposed in [6, 7], our approach to the ΣΔ architecture offers more flexibility due to the nature of the digital signal processing, and, moreover, it offers better IC integration. Synchronization between the envelope and phase signals is a critical point in this particular polar architecture. To
Figure 4: Architecture of the polar ΣΔ transmitter with digital mixing.
overcome this problem, it is suggested in this third approach to use a common reference frequency for the digital PLL and for the ΣΔ modulator. Multiplication of the ΣΔ modulated envelope and the modulated phase in the time domain corresponds to a convolution in the frequency domain. The output is then centred at 0, 3 f0 , 5 f0 , and so forth, and the quantization noise introduced by the ΣΔ modulator is symmetrical around the carrier.
3. Simulations of the Modified Polar ΣΔ Architecture: Mobile WiMAX Validation Mobile WiMAX is a very flexible wireless communication standard, which offers a choice among a range of different channel bandwidths that vary depending on the expected throughput and the allocated radio frequency band. The channel bandwidth may vary from 1.75 MHz to 20 MHz. The multi-radio architecture must support any of the configurations defined by the standard. This communication standard has been chosen in our simulations due to high envelope dynamics, relatively high channel bandwidths and very high requirements for the frequency synthesizer (in terms of integrated phase noise, frequency range, and settling time). The Mobile WiMAX operates at higher frequencies than any other cellular systems, and, hence, this fact draws the attention to the influence of the carrier frequency on the performance of the polar ΣΔ architecture. 3.1. Mobile WiMAX Technology. Mobile WiMAX standard supports mapping according to the QPSK, 16-QAM, or 64 QAM constellation schemes using the Orthogonal Frequency Division Multiplexing (OFDM) modulation. OFDMA air interface is based on the OFDM modulation and corresponds to the nonline of sight operation in licensed frequency bands below 11 GHz. The FFT size can vary between 2048, 1024, 512, and 128 [11]. Following parameters characterise the OFDMA: channel bandwidth BW, number of used subcarriers Nused and DC subcarriers, sampling factor n, and the cyclic prefix to useful time ratio G [11]. Channel bandwidths and the number of subcarriers are chosen depending on the selected frequency band, channel conditions, capacity, and the expected throughput. The factor n depends on the BW. Supported values for the G are 1/32, 1/16, 1/8, and 1/4. Certification profiles published by the WiMAX Forum
4
EURASIP Journal on Wireless Communications and Networking Table 1: Mobile WiMAX certification profiles [12, 14].
Frequency band (MHz) 2300–2400 2305–2320 2345–2360 2496–2690 3300–3400 3400–3800 3400–3600 3600–3800
Channel BW (MHz) 5 8.75, 10 3.5, 5 10 5 10 5 7,10 5
512 1024 512 1024 512 1024 512 1024 512
7,10
1024
FFT size
Settling time (μs)
E(z)
Phase jitter (◦ rms)
V (z)
+
H(z)
+
−
Figure 5: Model of a 1-bit ΣΔ modulator.
