Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996

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Low-Resistance Self-Aligned Ti-Silicide Technology for Sub-Quarter Micron CMOS Devices Tohru Mogami, Hitoshi Wakabayashi, Yukishige Saito, Tom Tatsumi, Takeo Matsuki, and Takemitsu Kunio

Abstruct- A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent preumorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-pn CMOS devices with low-resistance and uniform TiSi2 on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavilydoped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and sonrce/drain regions. Low-resistance and uniform TiSiz films were achieved on all narrow, long n+ and p+ poly-Si and diffusion layers of 0.15-pm CMOS devices. Ti& films with a sheet resistance of 5 to 7 R/sq were stably and uniformly formed on 0.15-pm-wide n+ and p+ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSir films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-pm NMOSFET’s and PMOSFET’s with self-aligned TiSi2 films.

1. INTRODUCTION HE production of MOSFET’s with low parasitic resistance in the gate electrode and sourceidrain diffusion layer is a key issue to achieve high-performance fine CMOS devices. Several structures with low parasitic resistance have been reported for CMOS devices. The polycide structure, in which the gate electrode consists of metal-silicide/poly-Si, has been widely used to reduce gate resistance without changing the gate design of MOSFET’s. However, in MOSFET’s with a polycide gate, the resistance in the sourceidrain region remains high and should be reduced. Self-aligned silicide (salicide) technology, which provides low-resistance silicide films on gate and sourceldrain regions, is one of the most important technologies in reducing the parasitic resistance in MOSFET’s [I]-[3]. In CMOS devices using the salicide process, sheet resistance of gate and source/drain regions can be reduced simultaneously. Furthermore, the salicide process is particularly suited to fabricating dual-gate CMOS devices [4]-[7], because simultaneous doping for the gate poly-Si and the sourcddrain diffusion layers can be carried out without an additional lithography process. Ti-silicide has very low resistivity [8] and is a very suitable material for use in the salicide process because of its easy silicidation and easy selective-etching of Ti and TIN [9]. Manuscript received September 14, 1995; revised December 5, 1995. The review of this paper was arranged by Editor K. Tada. The authors are with Microelectronics Research Laboratories, NEC Corporation. Kanaeawa 229. Jauan. Publisher hem Identifier S 0018-9383(96)04035-X.

However, it has recently been reported that it is difficult to form low-resistance TiSi2 on narrow (