IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
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Hot-Carrier Degradation Phenomena in Lateral and Vertical DMOS Transistors Peter Moens, Geert Van den bosch, and Guido Groeseneken, Senior Member, IEEE
Abstract—The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS. Index Terms—Charge pumping (CP), hot carrier, lateral integrated DMOS (LDMOS), vertical integrated DMOS (VDMOS).
I. INTRODUCTION
F
OR INTEGRATED smart-power applications, the capability of handling medium drain voltages (20–100 V) and current levels (2–10 A) needs to be combined with standard low-voltage CMOS logic cells. Typically, lateral DMOS transistors (LDMOS) are the devices of choice to accomplish this task as they are compatible with standard CMOS processing and can be easily integrated by the addition of some extra process layers. As such, LDMOS transistors are widely used and their electrical behavior is well documented (see [1]–[6] and the references quoted therein). A severe drawback of such lateral devices, however, is that the current is flowing at the Si/SiO interface making the devices vulnerable to hot-carrier injection and trapping [7]–[12]. An alternative is to use integrated vertical DMOS transistors (VDMOS). These devices, however, are less cost-effective to integrate because the current has to be collected at the surface of the silicon and not at the backside, as is the case in discrete devices. In smart-power technologies, this is accomplished by the incorporation of a highly doped n-type buried layer (BLN) to collect the current in the bulk of the silicon. A highly doped n-sinker is used to contact the BLN at the top surface. In this paper, the hot-carrier degradation behavior of a lateral and a vertical nDMOS transistor, processed in a 0.35- m compatible Intelligent Interface Technology [6], is presented. It will be shown that upon hot-carrier stress, two different and competing hot-carrier degradation mechanisms occur. The two mechanisms could be identified by analysis of the electrical Manuscript received September 9, 2003; revised January 6, 2004. The review of this paper was arranged by Editor M. A. Shibib. P. Moens is with AMI Semiconductor, Oudenaarde, B-9700, Belgium (e-mail:
[email protected]). G. Van den bosch is with Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, (e-mail:
[email protected]). G. Groeseneken is with Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, and also with Katholieke Universiteit, Leuven, Belgium (e-mail:
[email protected]). Digital Object Identifier 10.1109/TED.2004.824688
Fig. 1.
Device cross section of the lateral nDMOS. Lacc = 0:75 m.
data and by performing charge pumping (CP) experiments. Detailed TCAD simulations were also performed, supporting the proposed model. A first mechanism is attributed to a decreased electron mobility due to increased carrier scattering upon interface trap formation ( ) in the channel. The second mechanism occurs in the gate overlapped drift region or accumulation region of the device and is due to hot-hole injection and trapping. The presence and the competition of both mechanisms depends strongly on the stress conditions and on the type of device. II. DEVICE DESCRIPTION The devices investigated in this study are lateral and vertical nDMOS transistors processed in a 0.35 m CMOS compatible smart-power technology. The gate oxide thickness is 7 nm, which limits the maximum gate voltage to 3.6 V. The typical of gate voltage is 3.3 V. The off-state breakdown voltage both devices is around 85 V, with a specific on-state resistance ) of 0.21 and 0.16 mm for the LDMOS and the VDMOS ( measured at V and V). respectively ( The channel consists of the standard 0.35- m CMOS p-well. The devices are isolated from the p-substrate by a highly doped BLN. The on-state breakdown voltage (i.e., the drain voltage for ), which the intrinsic NPN transistor is triggered for a given is 74 V for the LDMOS and 82 V for the VDMOS. As a result, of 70 V, whereas the LDMOS can only be stressed up to a of 80 V, for the complete the VDMOS can be stressed up to a range of gate voltages. For a complete overview of the process flow and the definition of the different layers, we refer to [6]. The cross section of the LDMOS transistor is shown in Fig. 1. The most important layout parameters (channel length and gate overlapped drift region or accumulation region ), are indicated in the figure. The length of the field oxide in the
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Fig. 2. Device cross section of the vertical nDMOS. L
= 3:5 m.
drift region is optimized to obtain the necessary breakdown voltage. The cross section of the vertical nDMOS transistor is shown in Fig. 2. The current is flowing vertically in the lowly doped n-epi and is collected by the highly doped BLN and Nsinker. The epi thickness and concentration of the technology of the device is above 80 V, with are tuned such that the . The VDMOS also has an accumulation region minimum under the thin gate oxide. Note that for the VDMOS, two sources contribute to the current. Devices are measured in 20 bondpad frames in which all 16 devices have common gate, source, bulk and substrate contacts, but separate drain contacts. Constant bias channel hot-carrier stress experiments are performed at room temperature. During the stress, the relevant transistor parameters and the CP curves are measured at selected time intervals. CP experiments are perto V. The pulse formed by varying the CP base level from rise time and duration are 1 and 10 s respectively. The pulse height was fixed to 4 V, unless specified otherwise.
Fig. 3. Typical degradation characteristics of the most important electrical parameters for (a) the lateral DMOS (the device is stressed at V = 1:7 V and is measured at the stress conditions). (b) Vertical DMOS V = 65 V. I (stressed at V = 3:3 V and V = 70 V).
III. EXPERIMENTAL DATA Typical degradation characteristics of the most important electrical parameters for the LDMOS are shown in Fig. 3(a). V and V, which The device is stressed at corresponds to the maximum in the curve. The shift in threshold voltage is not depicted as it is very small (less than 2 mV). The transconductance and saturation current ( measured at the stress condition) first decrease upon stressing after which they appear to recover (typically between and s). The specific on-state resistance follows the opposite behavior. For many applications (current switches), is the most important device parameter. Hence, the the focus will be on the degradation of this parameter. The degradation characteristics for the electrical parameters ) are similar, with the exception that of the VDMOS (e.g., to s is not obthe recovery in degradation after about comserved [see Fig. 3(b)]. Instead, the degradation of the pletely saturates. This behavior is observed for all gate and drain stress conditions examined. CP measurements are performed by measuring the CP current ( ) at the bulk contact while pulsing the gate and grounding source and drain. The complete gate overlapped region of the device is pumped. Indeed, this region is the con-
Fig. 4. CP flatband and threshold voltages for the channel and accumulation regions of the DMOS transistors. Defined at n; p = 1e14=cm .
catenation of a standard nMOS transistor (channel area of the DMOS) and a pMOS transistor with an poly-gate (the gate overlapped drift region). This is valid for both the LDMOS and the VDMOS. The estimated CP “flatband” and “threshold” voltage levels of both transistors are shown in Fig. 4. These are the gate-pulse voltage levels needed to induce a majority resp. cm at the Si–SiO inminority carrier concentration of terface. Taking into account a pulse amplitude of 4 V, the CP signal for the pMOS is then expected between base levels of and V, whereas the CP signal for the nMOS should and V. appear at higher base levels between A typical CP characteristic is shown (on a logarithmic current scale) in Fig. 5. From the foregoing, it can be concluded that the small CP signal at low base level originates from the accumulation region, while the large signal is due to both channel and accumulation regions. Experimental verification for this is provided by a CP measurement with the drain left floating [13].
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Fig. 5. Typical CP curve obtained by measuring I at the bulk contact. The total CP signal is the sum of a signal attributed to the (dashed line) accumulation region and (dotted line) a signal attributed to the channel area. Note that the channel area CP signal is more than 10 times larger than the contribution coming from the accumulation area.
Fig. 6. CP curves measured with drain open and drain left floating. The differential signal is also plotted. The pulse height is 3 V.
This is shown in Fig. 6. In this case, the small CP component at low Vbase almost completely disappears. Indeed, when the drain is left floating, the necessary electrons have to be supplied at all times by the source of the transistor. No CP current will flow as long as the channel region is not inverted since no source electrons are able to reach the accumulation region. Once the channel region is inverted, the accumulation region can be flooded by source electrons, leading to CP in both regions. From then on a drain connection is no longer indispensable, illustrated more clearly in Fig. 6 by the differential signal going to zero. It should finally be noted that there is a strong disproportion between the channel and accumulation region contributions in the CP signal. This is due to the fact that the device under test is measured in a frame with common gate and source contacts. As a result, the CP signal unavoidably contains a constant contribution from all other 15 devices in the frame even when their drains are left open at all times. On the other hand, at low base level, the small signal from the accumulation region does require a drain connection and therefore can be uniquely attributed to the device under test. As such, the density of interface traps ( ) in both the channel and the accumulation regions can be extracted formation in the from the CP characteristics. The accumulation region is calculated from the CP signal at V, whereas the channel formation is V. For the latter extraction, the extracted at
Fig. 7. Time dependency of the hot-carrier degradation of the LDMOS for different stress conditions. (a) Degradation of the R . (b) Increase in N in the channel of the LDMOS. (c) Increase in N in the accumulation area of the LDMOS.
1
contribution of the 15 other devices in the frame has to be taken into account. The degradation of the of the LDMOS for different and values, is shown in Fig. 7(a). Fig. 7(b) and (c) depicts the time dependency of the incremental channel and accumulaformation upon stressing, respectively. For larger tion layer values, it seems that the turn-over point in degradation
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shifts to larger stress times. Also, the recovery seems to be less degradation pronounced at higher gate-stress voltages. The increases with drain-stress voltage. From Fig. 7(b) it follows that formation strongly saturates as from – the channel s. The formation in the accumulation region has a strong V, the dependency on the gate stress voltage: for formation in the accumulation region is about one decade V. Evidently, the smaller compared to stressing at turnover observed in the degradation of the electrical parameformation in the accumulaters is linked to the presence of both the turnover in the degradation tion layer: at high as well as the formation in the accumulation layer are much less. Additional evidence attributing the decrease in the degradation to accumulation layer formation is obtained from the VDMOS hot-carrier degradation and CP experiments, as is shown in Fig. 8. Fig. 8(a) shows the degradation of the of the VDMOS for different and , whereas Fig. 8(b) formation shows the corresponding incremental channel upon stress time. For the VDMOS, no formation in the accumulation region is observed, the contribution to the CP voltages is absent. From Fig. 8(a), it can signal at low completely saturates as be noticed that the degradation in from s. Also the channel formation saturates. The formation is in accordance with saturation of the channel the observation for the LDMOS [see Fig. 7(b)]. IV. DISCUSSION Out of the analysis of the degradation of the electrical parameters and the CP experiments for both the LDMOS and VDMOS, it follows that two different and apparently competing degradation mechanisms occur (competing as both ). mechanisms have an opposite effect on the shift of the A. Mechanism 1: Channel Mobility Reduction From the CP experiments, it follows that the first mechanism is due to interface state generation in the channel of the transistor. Hence, the mobility of the electrons is reduced, so also the current will decrease, and the will increase. The traps are assumed to be neutral, or at the drain side in the channel, is not affected. For both the LDMOS as well and so, the as the VDMOS, the interface state generation has the tendency to s. The complete satto saturate after approximately uration is very evident for the VDMOS, for the LDMOS the saturation in the degradation of the electrical parameters (e.g., ) is masked by the presence of a second mechanism. The formation in the LDMOS is found to be signiflevel of cm versus icantly higher compared to the VDMOS ( cm after of stress time). The maximum degradation in is accordingly larger in the LDMOS. For the is well VDMOS, the dependency of the first mechanism on dependency of the pronounced [see Fig. 8(a) and (b)]. The degradation, however, is weak. for the Another possibility to explain the increase in LDMOS would be the injection and trapping of hot electrons in the field oxide. Such charges are expected to lead to an increase
Fig. 8. Time dependency of the hot-carrier degradation of the VDMOS for different stress conditions. (a) Degradation of the . (b) Increase in in in the accumulation region of the channel of the VDMOS. No increase in the transistor is observed.
1N
R
1N
in and have no effect on . However, in this case no effect on the CP characteristics should be expected, as the field oxide is too thick to be accessible by CP [12]. In this paper, a clear correlation is found between the increase and saturation formation and the degradation of the . of the channel Moreover, a similar behavior is detected in the VDMOS, and this device has no field oxide in the drift region. B. Mechanism 2: Hot-Hole Trapping in the Accumulation Region (Gate Overlapped Drift Region) The second mechanism starts to show up in the hot-carrier – s of stress degradation data of the LDMOS after about time. From the CP experiments, this mechanism is located in the formation in the accumulation region of the transistor. The with beaccumulation region follows a power law values tween 0.3 and 0.4. No saturation is observed and up to cm are extracted, being larger than the formation observed in the channel. In contrast to the first mechain the accumulation region is comnism, the formation of pletely absent in the VDMOS transistor. From TCAD simulations it follows that the electric field across the thin gate oxide changes sign in the accumulation region, becoming favorable for hole injection. Fig. 9 compares the electric field component
MOENS et al.: HOT-CARRIER DEGRADATION PHENOMENA IN LATERAL AND VERTICAL DMOS TRANSISTORS
Fig. 9. Hole temperature and electric field perpendicular to the Si–SiO interface in the accumulation region of the LDMOS and the VDMOS (V = 2:0 V, V = 70 V). The length of the accumulation region for the LDMOS and the VDMOS is 0.75 and 3.5 m, respectively. Only half of the cell of the VDMOS is simulated as the structure is symmetric. The perpendicular electric field is negative indicating that the electric field vectors are pointing toward the oxide.
perpendicular to the gate oxide and the hole effective temperature for both the VDMOS and the LDMOS in the accumulation V and V. The data are taken region, for along a cutline 1 nm in the silicon, below the Si/SiO interface. m corresponds to the p-well–n-epi junction, i.e., the start of the accumulation region. Clearly, both the energy of the holes as well as the accelerating field toward the interface is much larger in the LDMOS. The maximum electric field is reached at the end of the accumulation region, i.e., at the beginning of the bird’s beak. For the LDMOS, the impact ionization spot is in the vicinity of the bird’s beak i.e., close to the surface. Hence the carriers still have a large energy at the Si/SiO interface. In the VDMOS the maximum impact ionization spot is further away from the Si/SiO interface, yielding less energetic carriers at the interface. The vertical distance of the maximum impact ionization spot is measured to be 0.35 m (at the bird’s beak) and 0.85 m for the LDMOS and VDMOS, respectively. A similar discussion holds for the electric field, where the presence of the bird’s beak in the LDMOS leads to a maximum in the electric field (see also Fig. 9). Therefore, it is believed that the probability of hole injection, and the subsequent formation of is larger in the LDMOS. Both the electric field and the hole energy are too low in the VDMOS to create interface traps. As such, the second mechanism is absent in the VDMOS transistor. In the LDMOS, the hole injection mechanism decreases with gate stress voltage [see Fig. 7(a) and (c)]. This can be understood by analyzing the variation of the maximum hole temperature in the accumulation region and the electric field perpendicular to , as is shown in Fig. 10. the Si–SiO interface as a function of Increasing the gate voltage will decrease both the electric field as well as the hole temperature. Hence, the carrier generation and injection mechanism will be reduced and as such the second mechanism will be less present at higher gate voltages. Injection and trapping of hot holes in the gate oxide of the accumulation region will result in a negative mirror charge in the top silicon of the accumulation region resulting in an effective will deincrease of the top n-epi concentration. Hence, the crease and the current will increase. For the LDMOS, holes are
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Fig. 10. Hole temperature and electric field perpendicular to the Si–SiO interface in the accumulation region of the LDMOS as a function of gate voltage (V = 70 V).
most likely to be injected near the tip of the source side bird’s beak, up to approximately 0.2 m away from the bird’s beak. is measured at low and high for which the As the current is confined to the surface, its measurement is believed to be sensitive to both degradation mechanisms in the LDMOS. For the VDMOS the current is at the interface until the end of the channel and is then redirected vertically into the silicon to be collected by the BLN. Thus, the current avoids the accumulation region and as such the electrical parameters are believed not to be able to sense the presence of interface trap generation in the accumulation region. From the CP experiments, it follows that is formed in the accumulation layer of the VDMOS. no V. CONCLUSION In this paper, the hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor has been investigated and compared. It is shown that two different and competing degradation phenomena exist in the LDMOS: channel formation and hot hole incarrier mobility degradation upon jection and trapping in the accumulation region. The first mechupon stressing, whereas the anism leads to an increase in . The latter mechanism second mechanism decreases the strongly decreases with increasing gate stress voltage. Due to the specific nature of the VDMOS device, the hot hole formation is injection is absent in this device. The channel substantially lower in the VDMOS. The hot-carrier degradation of the electrical parameters of the VDMOS completely saturates – s. after about An explanation of the observed features is given based on two-dimensional device simulations. ACKNOWLEDGMENT The authors wish to thank L. De Schepper and B. Vlachakis for their support in the CP and stressing experiments. REFERENCES [1] C. Y. Tsai et al., “16–60 V rated LDMOS show advanced performance in an 0.72 m evolution BiCMOS power technology,” in IEDM Tech. Dig., 1997, pp. 367–370. [2] V. Parthasarathy et al., “A 33 V, 0.25 m 3 cm n-channel LDMOS in a 0.65 m smart-power technology for 20-30 V operation,” in Proc. Int. Symp. Power Semiconductor Dev., 1998, pp. 61–64.
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[3] J. A. Van der Pol et al., “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., 2000, pp. 327–330. [4] T. Terashima et al., “Multi-voltage device integration technique for 0.5 m BiCMOS and DMOS process,” in Proc. Int. Symp. Power Semiconductor Dev., 2000, pp. 331–334. [5] Y. Kawagushi et al., “0.6 m BiCMOS-based 15 and 25 V LDMOS for analog applications,” in Proc. Int. Symp. Power Semiconductor Dev., 2001, pp. 169–172. [6] P. Moens et al., “I3T80: A 0.35 m based system-on-chip technology for 42 V battery automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., 2002, pp. 225–228. [7] A. W. Ludikhuize et al., “Analysis of hot-carrier-induced degradation and snapback in submicron 50 V lateral MOS transistors,” in Proc. Int. Symp. Power Semiconductor Dev., 1997, pp. 53–56. [8] R. Versari et al., “Hot-carrier reliability in submicron LDMOS transistors,” in IEDM Tech. Dig., 1997, pp. 371–374. [9] S. Manzini et al., “Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors,” in Proc. Int. Symp. Power Semiconductor Dev., 1998, pp. 415–418. [10] R. Versari and A. Pieracci, “Experimental study of hot-carrier effects in LDMOS transistors,” IEEE Trans. Electron Devices, vol. 46, pp. 1228–1233, Oct. 1999. [11] M. S. Shekar et al., “Hot electron degradation and unclamped inductive switching in submicron 60 V lateral DMOS,” in Proc. Int. Reliability Physics Symp., 1998, pp. 383–390. [12] P. Moens et al., “A novel hot-hole injection degradation model for lateral nDMOS transistors,” in IEDM Tech. Dig., 2001, pp. 877–880. [13] P. Heremans et al., “Analysis of the charge pumping technique and its applications for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, pp. 1318–1335, Oct. 1989.
Peter Moens received the M.Sc. and Ph.D. degrees in solid-state physics from the University of Gent, Gent, Belgium, in 1990 and 1993, respectively. From 1993 to 1996, he was a post-doctoral fellow in collaboration with Agfa-Gevaert, Mortsel, Belgium, on the electron capture efficiency of silver halide emulsions. In 1996, he joined AMI Semiconductor (formerly Alcatel Microelectronics), Oudenaarde, Belgium, where he is involved in the technology and device development for smart-power applications. His fields of interest are reliability-related aspects of integrated smart-power devices such as hot-carrier degradation and ESD issues.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 4, APRIL 2004
Geert Van den bosch received the M.Sc. degree in electrical and mechanical engineering in 1987 and the Ph.D. degree in applied sciences in 1993, both from the Katholieke Universiteit, Leuven, Belgium. In 1987, he joined the Interuniversity Microelectronics Center (IMEC), Leuven, where he did research on basic hot-carrier degradation effects, semiconductor device physics, and electrical characterization techniques. From 1993 to 1999, he was active in the development of several generations of deep-submicrometer mixed-signal CMOS technologies. Since 1999, his research has been covering the impact of process steps and modules on the yield and reliability of CMOS technologies, in particular issues such as plasma and process induced damage, hot-carrier degradation, ultrathin gate oxide integrity, and Cu–low- dielectric back end reliability. He is responsible for development and characterization of high-voltage devices and smart-power technology. Dr. Van den bosch served as the technical program committee member of the P2ID conference.
Guido Groeseneken (M’80–SM’95) received the M.Sc. degree in electrical and mechanical engineering in 1980 and the Ph.D. degree in applied sciences in 1986 both from the Katholiecke Universitat, Leuven, Belgium. In 1987, he joined the Research and Development Laboratory of the Interuniversity Microelectronics Center (IMEC), Leuven, where he is responsible for research in reliability physics for deep-submicron CMOS technologies. He has made contributions to the fields of nonvolatile semiconductor memory devices and technology, reliability physics of VLSI technology, hot-carrier effects in MOSFETs, time-dependent dielectric breakdown of oxides, ESD-protection and testing, plasma processing-induced damage, and electrical characterization techniques for semiconductors and high- dielectrics. He has authored or coauthored more than 200 publications in international scientific journals and in international conference proceedings, three book chapters, and seven patents in his fields of expertise. Dr. Groeseneken has served as a technical program committee member of several international scientific conferences, among which are the IEEE International Electron Device Meeting (IEDM), the International Reliability Physics Symposium (IRPS), and the IEEE Semiconductor Interface Specialists Conference (SISC). From 2000 to 2002, he also acted as the European Arrangements Chair of IEDM.
