High-speed polysilicon emitter—base bipolar transistor

658

VOL. EDL-7, NO. 12, DECEMBER 1986

LETTERS, DEVICE ELECTRONIEEE

High-speed Polysilicon Emitter-Base Bipolar Transistor HEE K. PARK,

h m m m , IEEE,

KIRK BOYER, CARL CLAWSON, MEMBER,IEEE, GREG EIDEN, ALEX TANG, TAD YAMAGUCHI, AND JACK SACHITANO

Abstract-High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VcE = 3 V, L VcEo = 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 pm, and a 1.3-pm-thick arsenicdoped LPCVD epitaxial layer of 0.25 Q . c m is utilized. Emitter-base (EB) junctions formed by direct implantations of arsenic and boron ions intoa substrate were comparedwithjunctions induced by diffusing dopants from implanted polysilicon. Indhe case of diffused junctions,an emitter junction depth of less than 500 A along with a 1000-A base width can be obtained.

substrate produced by a bird’s-beak-free planarized-refilledoxide (PRO)isolation scheme. The substrates used are p-( 111) silicon wafers of 40-100-0.cm resistivity in which a lithographicallydefined n + arsenic buried layer is formed by implantation and subsequent drive-in anneal. A 0.25-0 * cm epitaxial layer 1.3 pm thick is grown after defining n + buriedlayer regions. Device islands arephotolithographicallydefined and l .4 pm of the field area Si is anisotropically etched away by using a resist and oxide etch mask. After a channel stop implant and growth of a 1000-A buffer layer of oxide, a 2.2-pm-thick layer of CVDoxide is deposited and subsequently planarized. The first layer of undopedLPCVD HE USE OF polysilicon for base and emitter electrodes palysilicon is deposited, implanted with boron, and a 5000-A enables higher performance in Si bipolar transistors. This .plasmaCVDoxide is deposited.Afterdefiningoxide-poly is due to minimized collector-base parasitic capacitance when stacked layer patterns by reactive ion etching, a400-A the extrinsic basecontact is opened in the portion of the thermaloxide is grownprior to sidewalloxidespacer polysilicon baseelectrode that is over field oxide,and to formation to obtaina reliable Si-oxide interface under the narrowspacingbetween the self-aligned emitter and base sidewalloxide.The self-aligned poly-Si emitter contact is electrodes [1]-[6]. Compared to a conventional device struc- defined using an oxide box around the poly-Si base electrode, ture where the extrinsic base contact is placed on top of the minimizingemitter and basespacing as well as obtaining active device area, the polysilicon base electrodestructure will submicrometer emitter sizes without applying submicrometer typically reduce the collector-baseoverlaparea up to 60 photo patterns. Typically,a 4000-A -thick sidewalloxide percent. In addition, the use of a polysilicon emitter yields spacer is generated around the polysilicon base electrode. An forward current gain three to ten times higher than a direct HF dip treatment is carried out prior to the emitter poly-Si metal emitter contact [7], This enables increased dopingof the deposition, leaving no intentional interfacial oxide at the polybase to preventprematurepunchthrough whenusing the Siand substrate Si interface. The extrinsic basejunction is shallow base widths requiredfor high speed. Withthis process formed by diffusing boronfrom +e implantedp +-base technology, n-p-n silicon bipolar transistors have been re- polysilicon layer.Emitter and intrinsic base junctionsare ported to achieve fT of 9-17 GHz and sub-100-ps ECL gate formed either by diffusing dopants from implantedpolysilicon delays by numerous investigators [ 2 ] - [ 5 ] . Withminimized layers or by direct implantations of arsenic and boron into the collector-base parasitic capacitance, the effect of shallow substrate. Resulting emitter junction depth is 1400 and the emitter and base junctionsis even more important in realizing base junctiondepth is 3200 A for an implantedjunction high-speed devices. Oneprocesstechnique for achieving device. An emitterjunctiondepth of 500 A and less than shallower emitter-base (E-B) junctions is to form junctionsby 1000-A metallurgical base width can be obtained with a diffusion from an implanted polysilicon overlayer [6] which diffused E-B process, showing a peak concentration of 2 X we refer to as the diffused E-B process. We compared devices 10l8ions/cm3. ASIMS analysis with primary oxygenions was fabricated by this process to deviceshaving E-B junctions used in studying emitter-base junctionprofiles. A self-aligned implanted directly into single crystal silicon (implanted junc- TiSi2 layer is formedontop ofthe emitter polysilicon tion devices). Devices made with the diffused E-B process electrode andthis emitter polycide reducesthe sheet resistance resulted in very shallow junctions, superior E-B breakdown of (As -implanted and 2500- A -thick) emitter polysilicon characteristics, and higher speed. from 300 to 3-10 Wsq, with an arsenic implant dose of 3 x In this process,devicesare built on an oxide-isolated 1015-5x 10l5ions/cm2 [8]. This silicided second polysilicon is also used for short interconnect and undercrosses.The Manuscript received June 26, 1986; revised September 19, 1986. forward current gainof the silicided polysilicon emitter device The authors are with the Solid State ResearchLaboratory.Tektronix does not show any degradation when the polysilicon thickness Laboratories, Tektronix, Inc.. Beaverton? OR 97077. is enough ( > 2500A) to prevent the rough silicide/poly IEEE Log Number 8611526.

T

A

+

0741-3106/86/1200-0658$01.00 O 1986 IEEE

PARK et a[.: POLYSILICON EMITTER-BASE BIPOLAR TRAKSISTOR

659

TABLE I DEVICE PARAMETERS OF DIFFUSED EMITTER-BASE AND IMPLANTED EMITTER-BASE N-P-N POLY-SI

E-B TRANSISTORS

Diffused E-B

Implanted

E-B Emitter area

0 . 5 ~ 4wmz

0 . 5 ~ 4pm2

5,"

8.2 fF

8.2 fF

c,,,

7.8 fF

7.8 fF

Cjm hfe

17.2 fF 60

17.2 fF 100

Ll'ceo

6.8 volts

7 . 5 volts

Bveho

8.5 volts

3 volts

Bvcbo

19 volts

21 volts

Vear1y

20 volts

26 volts

Rb

400 ohms

ne

60 ohms ohms

70

Rc

220 ohms

300 ohms

Ft

15.6 GHz

9 GHz

Fmax

15.9 GHz

Xje

500

2E1S ~

N, (peak)

Fig. 1. SEM photographs of (a) cross-sectional and (b) top views of completed devices.

A

1400

I500 A

j ' h

3200 m - ~

A A

8E17 cm-'

0 VCE = 3 v

15

0 VCE

= 1v

interface from interfering with the single crystal Si emitter. i i . This self-aligned TiSiz layer can also be applied to reduce the . I base polpsilicon sheet resistance to less than Wsq. 3 For 10 resistors, boron implantation of the first polysilicon layer (R, of 100 Qisq, thickness 4000 A) was utilized. The temperature coefficient of this boron implanted resistor is 100 ppm in the temperaturerange of20-1 80°C. A 1-pm-thick platedAu metallization withTiW barrier is used for a final interconnect. 0 A cross-sectional view ofcompleted a device andtop a view of 1 0 - 0 , 2 5 100 100.25 100,5 100.75 101 101.25 101.5 a circuit, represented by scanning electron microscopy, are IC frnA) - . shown in Fig. 1, Fig. 2 . Cutoff frequency FT versus ICEwith V , , as a parameter. Solid line The dc characteristics Of the O.' x 4-/-4m2emitter represents diffused emitter-base and dashed line is for implanted emittersize transistor aresummarized in Table I. The saturation base. voltage V,,, varies from 130 mV for a 0.5 x 2-pm' device to 220 mV for a 0.5 x 20-pm2 device. The base resistance RB was measured by atwo-porttechnique [9] ai f = 12 GHz. The 25 C = M.A.G. loweremitter-baseleakagecurrent and higherbreakdown 20 voltages of diffusedemitter-basejunctionscompared to implantedjunctions indicate their high quality. CutofffreE quency f r versus collector current IC andcollector-emitter d j5 voltage VcEare obtained by measuring the S parameters over ~5 4 10 the 800-1300-MHzfrequencyrange using an HP 8505A 2 networkanalyzer with aCascadeMicrotechmicrowavewafer 5 probe station (see Fig.2).The test device consists of13 parallel 0.5 X 4-pm2transistors.Thepeak f T is obtained at a 0 currentdensity of about 370 ,uAlpm2 at VcE = 3 V. According to Fig. 2, the diffused emitter-base transistor with 10-0.25 100 100.25 100.5 100.75 101 101.25 WE = 0.5 pm shows f r o f 15.6 GHz at VCE= 3 V, whereas the implanted version exhibits 9 GHz, mainly due to its deeper FREQUENCY (GHZ) vertical junctiondepth.Fig.3 shows the frequencydepenFig. 3. Measured and MAG versus frequency curves.

IEEE ELECTROY DEVICE LETTERS. VOL. EDL-I, NO. 12, DECEMBER 1986

660

ACKNOWLEDGMENT The authors would like to thank E. Lane and J. Leefor fabricating devices and C. Bickford, D. Ahrendt, and A. Ueno for device measurement. Theauthors also wish to express their gratitude to S. Early for his helpful advice. REFERENCES

Fig. 4.

Output waveform of 21-stage ECL ring oscillator.

dence of maximum available gain (MAG) and S,, , the forward gain in a 5 0 4 environment (measured with an HP 85 10A from 500 MHz to 22 GHz). Extrapolating the 6-dB/octave portion of the MAG curve to the 0-dB gain axis yields f,,, = 15.9 GHz. Using 0.5 X 10-pm2 transistors, an ECL switching speedas fast as54.6 ps (FO = 1) has been obtained at a current density of 360 pA/pm2 with 4-pm metallization pitch. By using I X 2-pm2 transistors which were laid out to have 1pm overlap of polysilicon base and epitaxial collector, a 110ps gate delay has also been achieved at a current density of 200 pA/pmZ (8-pm metal pitch). Fig. 4 shows a typical output waveform of a 21-stage ECE ring oscillator with 0.5 X 10pm2 transistors. The internal logic swing is 450 mV.

D. D. Tang, P. M. Solomon. T. H. Ning, R. D. Isaac, and R. E. Burger, “1.25 pm deep-groove-isolated self-aligned bipolar circuits,” IEEE J. Solid-state Circuits, vol. SC-17, no. 5 : pp. 925-931, 1982. S . Konaka, Y. Yamamoto, and T. Sakai, “A 30 ps Si bipolar IC using super self-aligned process technology,” in Ext. Abstr. 16th Conf. Solid State Devices and Mater., 1984, pp. 209-212. M. Suzuki, K. Hagimoto, H. Ichino, and S . Konaka, “A 9-GHz frequency divider using Si bipolar super self-aligned process technology,” IEEE Electron Device Lett., vol. EDL-6, no. 4, pp. 181-183,

__

19x5.

M. Vora et al., “A sub-100 picosecond bipolar ECL technology,” in IEDM Tech. Dig., 1985. pp. 34-37. T. Tashiro et al., ‘*An 8 0 p s ECL circuit with high current density transistor,” in IEDM Tech. Dig. 1984, pp, 686-689. S. F. Chu et al., “A self-aligned bipolar transistor,” in Proc. VLSI Sci. Technol. 1982, pp.306-314. T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of silicon bipolar devices,” IEEE Trans. Electron Devices. vol. ED27. pp. 2051-2055. 1980. H.K.Park, .I. Sachitano, M. McPherson, T. Yamaguchi;and G. Lehman,“Effects of ion implantation doping on the formation of Ti&,” J. Vac. Sci. Technol. A , vol. 2 ? no. 2, pp. 264-268. 1984. I. Getreu, Modeling the Bipolar Transistor, Tektronix.Beaverton, OR, 1976,p.154. ~