High efficiency CMOS power amplifier for 3 to 5 GHz ultra-wideband (UWB) application

IEEE Transactions on Consumer Electronics, Vol. 55, No. 3, AUGUST 2009

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High Efficiency CMOS Power Amplifier for 3 to 5 GHz Ultra-Wideband (UWB) Application Sew-Kin Wong, Siti Maisurah, Mohd Nizam Osman, Fabian Kung and Jin-hui See

Abstract — A two-stage 0.18μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz using common source inductive degeneration is presented in this paper. Onwafer measurement shows an average power gain of 15.2 dB with gain flatness of 0.6 dB and an input 1 dB compression (P1dB) above − 6.1 dBm from 3 to 5 GHz while consuming 25 mW from a 1.8 V supply. Load-pull measurement also shows a power added efficiency (PAE) of 34% at 4 GHz with 50Ω load impedance. Results obtained in this work could be used as a reference design for immediate PA implementation in commercial mobile or portable UWB transmitter or signal generator.1 Index Terms — Ultra-Wideband (UWB), Power amplifier (PA), UWB CMOS PA.

I. INTRODUCTION Ultra-wideband (UWB) system, as compared to Bluetooth and WiMax has emerged as a new technology capable of offering high data-rate and wide spectrum of frequency (low frequency band from 3.1 to 5 GHz and high frequency band from 6 to 10.6 GHz) with very low power transmission [1]. Currently, two major solutions in the IEEE 802.15.3a are proposed to transmit data up to 480 Mbps, namely the multiband orthogonal frequency division multiplexing (MBOFDM) UWB and direct-sequence code division multiple access (DS-CDMA) UWB [2]. For the first generation UWB system deployment, both approaches use a low frequency band of 3.1 to 5 GHz as a mandatory mode. The primary applications for UWB as proposed by WiMedia Alliance [3] are general cable-replacement and short range high data rate communications for consumer electronics such as digital cameras, laptops, and cell phones. WiMedia UWB will also serve as the underlying transport protocol for Wireless USB and Bluetooth 3.0. The power amplifier (PA) circuit remains as one of the challenging tasks in transmitter design as it must meet several stringent requirements such as broadband input matching, high power gain, suitable output power and reasonable efficiency for low power consumption. Various topologies

have been used in the implementation of wideband amplifiers, such as the resistive shunt feedback topology [4] and the RLC matching topology [5]-[8]. Generally, the choice of topology used depends strongly on the requirement of the amplifier and its additional features such as power control, linearity and efficiency. In this study, a two-stage common source (CS) inductive degeneration PA for UWB transmitter using 0.18μm CMOS process is proposed. To ensure reasonable gain and high power efficiency, the first stage of the PA is optimized for maximum gain using a cascode structure while the second stage is a simple CS topology designed for maximum output power. The design consideration and on-wafer (die) measurement results of the implemented 3 to 5 GHz UWB PA are also presented. This paper is organized as follows. Section II describes the overview of the PA circuit design. Basic analytical equations are used in order to calculate the required circuit parameters. The chip layout and measurement results for the proposed PA in a 0.18μm silicon CMOS process are reported in Section III. Finally, Section IV presents the conclusion of this work. II. UWB PA CIRCUIT DESIGN In this work, the proposed PA relies on a two-stage amplifier in order to achieve optimum output power and gain while maintaining a wide bandwidth. The proposed two-stage PA is shown in Fig. 1. This PA employs a cascode topology on first stage with a current mirror circuit while second stage is a simple CS stage without cascode transistor and Lg. The proposed PA is initially targeted at a power consumption of 30 mW from a 1.8 V dc supply. This gives the total drain current of approximately 17 mA, to be distributed over the two-stage PA. Assuming a current of 7 mA to be drawn by M1 for first stage, the calculated size for transistor M1 is approximately 80 μm based on the following equation [9]: I DD ≈

W 1 μ n C ox (VGS1 − Vt )2 L 2

(1)

where VGS1 = 0.8 V, Vt = 0.5 V, μ n = 0.03903 m2/V-s and Cox 1 This work was supported by Intel Technology Sdn. Bhd., Malaysia, under Intel research grant 2005-07. Sew-Kin Wong and Fabian Kung are with Faculty of Engineering, Multimedia University, Jalan Multimedia, 63000 Cyberjaya, Selangor, Malaysia (e-mail: [email protected]; [email protected]). Siti Maisurah and Mohd Nizam Osman are with Telekom R&D, Malaysia. (e-mail: [email protected]; [email protected]). Jin-Hui See is with Intel Sdn. Bhd., Malaysia (e-mail: [email protected]).

Contributed Paper Manuscript received July 6, 2009

= 0.00946 F/m2, for a typical 0.18μm silicon CMOS process. The required transconductance, gm1 can be further determined by the following equation [9]:

g m1 =

0098 3063/09/$20.00 © 2009 IEEE

∂I DD W⎤ ⎡1 = 2⎢ μ n C ox ⎥ (VGS1 − Vt ) L⎦ ∂VGS1 ⎣2

(2)

S.-K. Wong et al.: High Efficiency CMOS Power Amplifier for 3 to 5 GHz Ultra-Wideband (UWB) Application

1 W I DD / [ μ n C ox ] and 2 L substituting into (2), the equation for gm1 can be simplified to:

(VGS1 − Vt ) =

Rearranging (1) to

g m1 = 2

1 W μ n C ox .I DD = 2 β .I DD 2 L

(3)

1 W μ n C ox is known as transconductance 2 L parameter. Hence, the calculated gm1 is approximately 47.9 mA/V. By ignoring the Miller effect of gate-drain capacitance (Cgd1) of transistor M1, the input impedance of M1 is given by [9]:

where

β=

Z in1 = jω ( Lg1 + Ls1 ) +

g L 1 + m1 s1 jωC gs1 C gs1

(4)

where gm1 and Cgs1 are the transconductance and the gatesource capacitance of M1. Inductors Ls1 and Lg1 are the source degeneration inductor and the gate input inductor. The real part of the input impedance in (4) is given by: Re{Z in1} =

g m1. Ls1 C gs1

(5)

With given values of gm1 and Cgs1, the desired impedance to match to Rs (usually 50Ω) can be obtained by setting Ls1 accordingly. Next, the imaginary part of the input impedance can be compensated with an input matching inductance Lg1. The corresponding resonance frequency is approximated by:

ω0 ≈

1 ( Ls1 + Lg1 )C gs1

1547

a current of 10 mA to be drawn by M3 for second stage, the calculated size for M3 is approximately 110 μm, based on (1). In general, a large transistor size M3 is needed to provide high gain and output power of the amplifier at high frequency. However, large transistor size usually has high parasitic capacitance and transconductance, which will increase the power consumption [10]. Therefore, the size of M3 is optimized at 160 μm for reasonable power consumption. The overall biasing network of the PA is formed by four resistors Rb1 to Rb4 and two current mirror transistors M4 and M5. The current mirrors are set by the supply voltage (Vdd) and large biasing resistors in conjunction with the gate bias, Vgs of both M1 and M3. A large value of Rb2 is used as RF choke to provide RF signal isolation from the input. Depending on the amount of bandwidth and noise required, these biasing resistors can be varied accordingly to provide their conventional roles of flattening the gain over a wide bandwidth. In order to provide sufficient RF shunting, five large on-chip capacitors (Cb1 to Cb5) are included in the circuit. Finally, dc blockings are provided by capacitors Cin, Cint and Cout. The proposed design are simulated and optimized with Agilent Technologies’s Advanced Design System (ADS) software before CMOS IC layout and fabrication. BSIM (Berkeley Short-channel IGFET Model) signal model version 3.3 is used for the CMOS transistor modeling and the passive on-chip components (spiral inductors, metal-fingered capacitors, pads and interconnects) are modeled by RLC equivalent networks in the circuit schematics. Thus, all relevant parasitic values are taken into account for circuit simulations.

(6)

The source degeneration inductor Ls1 is added for linearity and stability improvement where as Lg1 is needed for the impedance matching between the source impedance and the input of transistor M1 [9]. In this design, the value of Ls1 is chosen to be small enough (approximately 0.5 nH) so that it could be easily replaced by a bondwire inductance in order to reduce the chip area when necessary. Next, the value of Lg1 is calculated from (6) to be approximately 3 nH using a resonance frequency of 4 GHz. A cascode transistor M2 is placed after M1 in order to provide a large active load for voltage gain improvement in the first stage. An inductor Ld1 of approximately 4 nH is placed as shunt peaking inductor resonating with its parasitic capacitances at the drain of transistor M2 around 4 GHz. A large value of peaking inductance (Ld1) is necessary in order to compensate the power consumption. It is also used as RF choke to the DC supply. A CS stage with similar configuration (without cascode transistor and Lg) is added to further improve the gain of the PA. Using the same procedures as the first stage and assuming

Fig. 1. Schematic of the proposed two-stage UWB PA.

III. EXPERIMENTAL RESULTS The proposed PA has been fabricated in Silterra Malaysia Sdn Bhd 0.18μm CMOS process with testing pads. The die microphotograph is shown in Fig. 2, with a size including pads of 1.1 mm × 1.5 mm. Metal-fingered capacitors and spiral inductors and used in this layout.

IEEE Transactions on Consumer Electronics, Vol. 55, No. 3, AUGUST 2009

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3 to 5 GHz when the drain voltage drops to 1.5 V. Table 1 show measurement summary and comparison with other literatures. 20

S21

Magnitude S-parameters (dB)

10

Fig. 2. Die micrograph of the PA (1.1 mm × 1.5 mm).

S11

S22

-20 -30 -40

S11 S21 S12 S22

-50 S12

-60 -70 1

2

3

4 5 Frequency (GHz)

6

7

8

Fig. 3. Measured S-parameters. 17 16.5

Input P1dB at 4 GHz = -3.4 dBm

16 15.5

|S21| (dB)

On-wafer measurements are carried out for power gain, return losses and 1dB gain compression (P1dB). For accurate power added efficiency (PAE) measurement [11], active loadpull system is used. Small-signal measurements were conducted using vector network analyzer, in which shortopen-load-thru (SOLT) calibration was performed at the probe tips using standard Alumina calibration substrate. All system power losses (wafer probes, cables and connectors) are calibrated out with a through measurement (through standard from using calibration substrate). The measured small signal S-parameter data are shown in Fig. 3. As shown here, the PA has a gain of approximately 15.2 ± 0.6 dB over the 3 to 5 GHz frequency range while maintaining a 3-dB bandwidth of 2.6 to 5.4 GHz. The maximum input and output return losses at 4 GHz are 5 dB and 6 dB respectively. The input and output return losses can be further improved by using external components if necessary. The PA also achieved a good reverse isolation of more than 30 dB over the range of 1 to 8 GHz. Using the measured S-parameter data, the stability factor (K) is also computed and its value is larger than 1 (unconditionally stable) across the interested frequencies, ranging from 1 to 8 GHz. The P1dB measurement is depicted in Fig. 4. Here, the input P1dB for the PA at 3, 4 and 5 GHz are −3 dBm, −3.4 dBm and −6.1 dBm respectively. The load-pull contours at 4 GHz for PAE and output power measurements is shown in Fig. 5. Here, the PA achieved an output power up to +11.2 dBm and PAE of 34% in a 50 Ω load. The efficiency and output power of the PA can be increased to 43% and +12.6 dBm if an 83 + j50 Ω load termination is used at the output. The PAE measurement is shown in Fig. 6. At P1dB, the PA has an efficiency of approximately 32% at 3 GHz, 34% at 4 GHz and 14% at 5 GHz respectively with 50 Ω load termination. The small signal gain versus the input power for 3 to 5 GHz is depicted in Fig 7. Across the 3 to 5 GHz frequency range, the optimum input power without 1 dB gain compression is approximately −6 dBm. The variation of small-signal gain with different supply voltages is shown in Fig 8. This PA could maintain an average gain of approximately 14 dB across

0 -10

Input P1dB at 5 GHz = -6.1 dBm

15 14.5

Input P1dB at 3 GHz = -3.0 dBm

14 13.5

P1dB@3GHz

13

P1dB@4GHz

12.5

P1dB@5GHz

12 -18

-16

-14

-12

-10 Pin (dBm)

-8

-6

-4

Fig. 4. Measured input P1dB at 3, 4 and 5 GHz.

Fig. 5. Measured Load-pull contours at 4 GHz (at P1dB = −3.4dBm).

-2

S.-K. Wong et al.: High Efficiency CMOS Power Amplifier for 3 to 5 GHz Ultra-Wideband (UWB) Application 16.0

70 PAE@3GHz PAE@4GHz PAE@5GHz

60

Vdd = 1.8V

15.5

50 |S21| (dB)

15.0

40

PAE (%)

1549

PAE@4GHz = 34%

30

PAE@3GHz = 32%

20

14.5 Vdd = 1.5V 14.0

PAE@5GHz = 14%

|S21| at Vdd = 1.5V |S21| at Vdd = 1.6V |S21| at Vdd = 1.7V |S21| at Vdd = 1.8V

13.5

10

-3.4

-6.1

-3

13.0

0 -18

-13

-8 Input Power (dBm)

-3

3

2

3.5

4 Frequency (GHz)

4.5

5

Fig. 8. Measured small signal gain (|S21|) vs. drain voltage (Vdd).

Fig. 6. Measured PAE for 3, 4 and 5 GHz at 50 Ω load impedance.

IV. CONCLUSION

A 0.18μm CMOS UWB PA for lower band UWB system (3 to 5GHz) is simulated and measured in this work. By using a two-stage CS inductive degeneration topology, the proposed PA achieved a +15.8 dB gain, 0.6 dB gain flatness, +11.4 dBm of output 1 dB compression and up to a maximum of 34% power efficiency at 4 GHz using a 50 Ω load termination, while consuming only 25 mW. The proposed circuit occupy an area of 1.1 mm × 1.5 mm. According to the measured results, the proposed PA has the highest efficiency and output power among the reported UWB PA to date. It is very useful for low band UWB transmitter implementation especially for mobile or portable devices using UWB system.

17.0 Input power = -12 16.0 P1dB

|S21| (dB)

15.0 14.0 13.0

Input power = -2 dBm |S21| at Pin = -2dBm |S21| at Pin = -4dBm |S21| at Pin = -6dBm |S21| at Pin = -8dBm |S21| at Pin = -10dBm |S21| at Pin = -12dBm

12.0 11.0

ACKNOWLEDGMENT

10.0 3

3.5

4 Frequency (GHz)

4.5

5

Fig. 7. Measured small-signal gain (|S21|) vs. input power (Pin).

The authors would also like to thank Silterra Malaysia Sdn Bhd for chip fabrication and Telekom R&D Malaysia for the load-pull measurement.

TABLE I COMPARISON OF WIDEBAND CMOS PA PERFORMANCES: PUBLISHED AND THE PRESENT WORK Ref.

3dB BW

S11

S22

Gain@4GHz

P1dB@4GHz

PAE@4GHz

Power

Area

(GHz)

(dB)

(dB)

(dB)

(dBm)

(%)

(mW)

(mm2)

[5]

3.1 to 4.8

< −10

< −8

19

−22.0 (input)

[6]

3.1 to 10.6

< −9

< −8

15

[7]

3 to 12

< −10

< −8

[8]

3 to 4.6

< −10

This work

2.6 to 5.4

< −5 *

Remarks

N/A

25

1.9 x 1.1

Cascode 1-stage with 3 transistors & 7 spiral inductors

0 (output)

N/A

25.2

1.1 x 1.0

Cascode 2-stages with 4 transistors and 4 spiral inductors

10.46

+5.6 (output)

N/A

84

2.3 x 0.76

Cascode 4-stages with 8 transistors & 16 spiral inductors

< −10

17.5

+0.42 (output)

3.9%

N/A

1.57 x 0.97

Cascode 2-stages with 4 transistors & 5 spiral inductors

< −6 *

15.8

−3.4 (input)

34% **

25

1.1 x 1.5

Cascode-CS 2-stages with 5 transistors and 5 spiral inductors

−4.2 (output)

+11.4 (output)

* can be improved by off-chip matching component during implementation, if necessary ** Value measured with active load-pull system, at input power of −3.4 dBm with 50Ω load impedance

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REFERENCES [1]

‘Final Rule of the Federal Communications Commission, 47 CFR Part 15, Sec. 503’, FCC, Federal Register, vol. 67, no. 95, May 2002. [2] WPAN High Rate Alternative PHY Task Group 3a (TG3a), IEEE 802.15, 2007 [Online]. Available: http://www.ieee802.org/15/pub/ TG3a.html. [3] ‘MultiBand OFDM Physical Layer Specification’, WiMedia Alliance, July 2005. [4] C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim and S. G. Lee, “An ultra wide-band CMOS low noise amplifier for 3-5 GHz UWB System,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 544-547, Feb. 2005. [5] S. Jose, H-J. Lee, D. Ha and S.S. Choi, “A Low-power CMOS Power Amplifier for Ultra wideband (UWB) Applications,” in Proc. IEEE International Symposium on Circuits and Systems, 2005, pp. 51115114. [6] C.H. Han, W.W. Zhi and K.M. Gin, “A Low Power CMOS Full-Band UWB Power Amplifier Using Wideband RLC Matching Method,” in Proc. IEEE Electron Devices and Solid-State Circuit Conf, 2005, pp. 223-236. [7] C. Lu, A.-V. Pham and M. Shaw, “A CMOS Power Amplifier for FullBand UWB Transmitters,” in Proc. IEEE RFIC Symp., 2006, pp. 397400. [8] R-L Wang, Y-K Su and C-H Liu; “3~5 GHz Cascoded UWB Power Amplifier,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp 367-369. [9] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. New York: Cambridge Univ. Press, 2004. [10] S. Andersson, C. Svensson, and O. Drugge, “Wideband LNA for a Multistandard Wireless Receiver in 0.18um Process,” in Proc. European Solid-State Circuits Conf., 655-658, Sep. 2003. [11] A. Ferrero, V. Teppati and A. Carullo, “Accuracy Evaluation of OnWafer Load–Pull Measurement,” IEEE Trans. on Microwave Theory and Techniques, vol. 49, no. 1, pp. 39-43, Jan. 2001.

Sew-Kin Wong received the B.Eng degree from University of Science Malaysia in 1995 and M.Eng.Sc degree from Multimedia University Malaysia in 2003. He is currently pursuing a Ph.D. in Faculty of Engineering at Multimedia University, Malaysia. His research interests are RF transceiver design for the next generation wireless systems.

Siti Maisurah received her B.Eng and MEng.Sc degrees from Multimedia University Malaysia, in 2003 and 2009 respectively. She is currently working with Telekom Research and Development Malaysia Sdn Bhd. Her research interests include RFIC design and power amplifier design for UWB system.

Fabian Kung received the B.Eng. and M.Eng.Sc. degrees from the University of Malaya, Malaysia, in 1994 and 1997, respectively, and the Ph.D. degree from the Multimedia University, Malaysia, in 2003, all in electrical engineering. He is currently a member of the Faculty of Engineering, Multimedia University.

Mohd Nizam Osman received his B.Eng. from Uniten in 2001 and M.Sc. from UiTM in 2009. He started his first job in 2001 as a design engineer at Sony Technology (M) Sdn. Bhd. He then joined TM Research & Development Sdn. Bhd in 2004 as a researcher which is currently working on the design and fabrication of MMIC using GaAs technology. His research of interest is more on the RF and Microwave device characterization for high frequency telecommunication applications.

Jin-Hui, See received B. Eng degree from Nanyang Technological University Singapore in 1999. He is currently working with Intel Microelectronics (M) Sdn Bhd