Generalized optical logic elements – GOLEs

Optics Communications 271 (2007) 365–376 www.elsevier.com/locate/optcom

Generalized optical logic elements – GOLEs H. John Caulfield a, Richard A. Soref b, Lei Qian a, Andrey Zavalin b

a,*

, James Hardy

c

a Fisk University, 1000 17th Avenue, N., Nashville, TN 37208, United States Air Force Research Laboratory, Sensors Directorate, Hansom AFB, MA 0173, United States c Idaho State University, 921 South 8th Avenue, Pocatello, ID 83209, United States

Received 27 March 2006; received in revised form 25 September 2006; accepted 20 October 2006

Abstract A Generalized Optical Logic Element or GOLE is device that performs any of the 16 Boolean logic operations on signals in an optical beam with very fast switching among functions. The advantages of a generalized or universal gate in manufacturing are obvious. Extremely flexible functioning becomes possible if the GOLE functionality is switched in response to earlier computations. Likewise Field Programmable Gate Arrays or FPGAs can be used to fix the GOLE functions, making one of the most powerful and flexible processor units ever designed – called a Field GOLE. Such systems can be made in bulk optics to utilize Spatial Light Modulator or SLM capabilities, but integrated optics on silicon will be the choice for most applications. GOLEs can be generalized in several ways to become Fredkin gates and generalized Fredkin gates. They can also be cascaded similarly to electronic gates.  2006 Elsevier B.V. All rights reserved.

1. Introduction Optical logic elements with switchable functionality have been discussed in the past. These are optical logic gates that can implement any logical function. Their electronic counterparts are things like FPGAs (Field Programmable Gate Arrays) and PLAs (Programmable Logic Arrays). The earliest work on optical PLAs was due to Morozov. The only English language version of this work is [1]. This was quickly followed by work of Guilfoyle and others [2–4]. A totally different approach is called ‘‘symbolic substitution.’’ It works in parallel (a strength of optics) on arrays of binary (on–off) pixels (picture elements). When a particular pattern is recognized in the input plane, a look up table causes it to be replaced by another pattern in the output plane. This approach can implement any logical operations [5–7]. The work on generalized or universal optical logic gates that can be rapidly reprogrammed to implement any logical function has only recently begun. This is analogous to *

Corresponding author. Tel.: +1 615 397 6743; fax: +1 615 329 8634. E-mail address: azavalin@fisk.edu (A. Zavalin).

0030-4018/$ - see front matter  2006 Elsevier B.V. All rights reserved. doi:10.1016/j.optcom.2006.10.051

elements of an FPGA. The only published work to date is [8]. This work is a continuation and elaboration of that paper. While Caulfield et al.’s paper [8] is the first in generalized optical logic, it points back toward earlier work on interferometric conservative optical XOR/COINC gates [9,10]. Those earlier papers, however, did not make the two critical insights necessary for the construction of the GOLEs described here and in [8]. Those insights are as follows: 1. An interferometer (without loss of generality, think of it as a Mach-Zehnder interferometer that has such distinct input and output pairs) can be viewed as a single stage Digital Light Deflector or DLD (see Appendix A). One input beam is switched to one of two possible output positions depending on its phase relationship with a second mutually coherent ‘‘control beam.’’ Indeed, all of the light goes into the selected beam. This is the only pure case of light switching light known to us. N layers of DLDs give a system, which produces one of 2N output positions depending on the values of N switches [11–14].

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2. Such interferometric DLDs can be used as LUTs or Look Up Tables. While the use of DLDs for optical logic appears to be new, a related concept was discussed by Tanida et al. [15]. They used fixed birefringent plates to create four beams from one and distinct spatial operations in each. We have amassed over 850 papers in for our research on optical logic and systematically searched them for related work. Tanida’s is by far the closest work to ours. Some logic operations have been performed using directional couplers – a kind of interferometer suitable for integrated optical GOLEs. Benner [16] even makes the switching optical through a photoconductive device. So, indirectly, through the mediation of non-optical materials, light switches light. His gates are not used to create LUTs, however they could be. With those insights in place, implementing conservative logic operations became possible but was not discussed in [8]. We will deal with such a system here. The gates in [8] and those emphasized here are dissipative. They are not always reversible. For a more extensive discussion of conservative vs. dissipative optical logic gates see [17–19]. Next, we will introduce some variants of the basic system. One variant is the conservative logic version of which [8] is a special case. Then, we will discuss both bulk optical implementations using SLMs and integrated optical implementations emphasizing silicon photonics. Thereafter, we turn to the logic itself, showing its limitations and ways around some of them. We conclude with an analysis of the potential for GOLEs and Field GOLEs for solving practical problems.

Fig. 2. The two beams used as input in Fig. 1 can be generated as shown here.

The drawings become more intuitive, if we represent such interferometers as ‘‘black boxes’’ having one (Fig. 2) or two (Fig. 1) inputs and two outputs. Now it is clear that two stages of such a DLD will allow the entire incident light to go into one of four output positions according to the phases of the beams as suggested in Fig. 3 using the box diagrams just suggested. Now let us simplify the drawing even more, by showing only the input beam, the four output beams, and the two control signals. Fig. 4 shows that simplified version of Fig. 3 (itself simplified as described above). But, just as clearly, this system works backwards as a Digital Light Combiner (DLC). A two stage DLD followed by a two stage DLC using the same controls as the DLD will recombine all of the light into a single beams as suggested in Fig. 5. It has surely occurred to most readers that the DLD– DLC system of Fig. 5 is a very elaborate way of accomplishing absolutely nothing. This is what we have called elsewhere a do-nothing machine [20]. They are very valuable, because interesting things tend to happen when you

2. GOLEs and their variants

C2

2.1. Conservative transmissive GOLEs The idea is to convert an interferometric DLD into a LUT, specifically a truth table, whose entries are readily modified. Because it is easy to draw, consider a directional coupler as the interferometer. Depending on the relative phases of the two input beams, we can arrange that device so that all of the light comes out the top line with one phase and out the bottom line with the other as suggested in Fig. 1. To generate two beams and control their relative phases, we need an initial interferometer as suggested in Fig. 2.

C1

C2

Fig. 3. All of the incident light comes out one of the four output positions depending on phases or phase controls C1 and C2.

C1

C2 (1,1) (1,0)

I (0,1) (0,0) Fig. 1. A directional coupler can be made to function as a single stage DLD. Depending on the relative phase of the control C to the signal S, all of the light from both beams will emerge from one of the two output positions. For the first time known to us explicitly, light is viewable as directly switching light. Accordingly, this operation is conservative.

Fig. 4. Simplified drawing of Fig. 3. Following the Fig. 3, if C1 = 0 the light from the first module goes into the lower path. If C2 = 1, the light from the second module goes into its upper position. So the control vector (0, 1) has a unique output position (as do the other three control vectors).

H. John Caulfield et al. / Optics Communications 271 (2007) 365–376

C1

C2

C2

367

C1 I0 I1

DLC

DLD

I3

Fig. 5. A DLD followed by a DLC can be configured to direct all of the input light into a single output position simply by using the same control signals in both.

perturb or filter the signals in intermediate positions. In this case, we can place a filter in the intermediate plane that passes only the light indicating the truth of the selected logical function of C1 and C2. For example, blocking all but the top beam (1, 1) implements an AND gate. Blocking only the top beam produces a NAND gate. This is clearly dissipative, as (for example) we have no idea where the light went that got blocked in the AND gate. Nevertheless it is a GOLE (Generalized Optical Logic Element), because it can be tasked to perform any of the 16 Boolean logic gates. 2.2. Reflective GOLEs In principle, reflective GOLEs are even easier to make than transmissive GOLEs. Fig. 6 sketches the idea. This is more compact than the transmissive version and can result in light loss unless polarization is used to distinguish between beams traveling the two directions and a polarization beamsplitter is employed. 2.3. Conservative transmissive/reflective GOLEs Now consider combining the last two GOLE designs with a filter that is selectably transmissive or reflective. No information is thrown away, so the system is conservative. 2.4. A variant GOLE architecture GOLEs do not have to be built around Do-Nothing Machines. Shown in Fig. 7 is an entirely different geometry for a GOLE. It is programmed by the pattern of input beams (Taking the place of the pattern of ‘‘holes’’ in a transmissive mask, for example). This is virtually a typical C1

O

I2

C2

IN DLD/DLC

MIRROR

OUT Fig. 6. A mirror converts a DLD into a DLC producing a do-nothing machine. A filter in the plane of the mirror converts this system into a GOLE.

C0

C1

Fig. 7. Any one of the four outputs of Fig. 22 device becomes a LUT (Look Up Table).

lookup table. There is only one logical function of C0 and C1 that will take that pattern of ‘‘on’’ and ‘‘off’’ inputs to the one output. This is too a physical embodiment of the Truth Table for any of the 16 Boolean logic functions. More specifically, to make the output O be a function, say f, of C0 and C1 (that means f(C0, C1) = O), we simply let I0 = f(0, 0), I1 = f(0, 1), I2 = f(1, 0), I3 = f(1, 1). For example, to make O = C0ORC1, we can make I0 = 0 and I1 = I2 = I3 = 1 because C0ORC1 = 0 only when both C0 and C1 are 0. To make the DLD be an AND gate, we can let I0 = I1 = I2 = 0 and I3 = 1. In addition, in Fig. 22 other three outputs O1, O2 and O3 also define logical functions of C0 and C1. More specifically, if O0 = f(C0(0), C1(0)), then O1 = f(C0 (0), C1(1)), O2 = f(C0(1), C1(0)) and O3 = f(C0(1), C1(1)). Comparing to the construction before, four inputs I0 through I3 need not be generated from a single source and the controls C0 and C1 all just have to apply to one level rather than to two levels. 2.5. Extending single GOLES to field GOLEs FPGAs (Field Programmable Gate Arrays) and PLAs (Programmable Logic Arrays) have proved tremendously useful as what amounts to an intermediate system between boards fabricated using discrete parts and ASICs (Application Specific Integrated Circuits). They can perform different functions depending on how they are interconnected, and the interconnection is facilitated by the design. That raises the question of whether it might be possible to use GOLEs in such a system. The advantages of what we will call a Field GOLE – a field programmable array of GOLEs – is easy to state in principle: They would be the most flexible field programmable systems ever made, because the components being interconnected no longer have fixed functionalities. Each GOLE can have one of 16 possible functions. One way of assembling a Field GOLE is shown in Fig. 8. This particular arrangement can do many things including mapping into a minterm of a PLA if the GOLE controls are set to perform an AND operation. For readers who are not familiar with this concept, we illustrate with a function f of three variables: x, y, and z. Suppose we want

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Controls (Electronic)

GOLE 1

GOLE 2

...

GOLE N

Data (Optical or Electronic) Fig. 8. This shows one of many ways to assemble a Field GOLE Fig. 17. A simple linear array of GOLEs can be a Field GOLE. The controls fix the functions for each GOLE. The light flows from one to the other if and only if all prior GOLEs have represented true propositions.

to implement any arbitrary f such as the one shown in the truth table (Table 2). Every one of the 28 = 128 different ways of placing 1s and 0s in the last column is a different logical function. This one, that has no known significance, is true only if Line 2 or Line 4 of the truth table is instantiated. Line 2 is true if (x AND y AND z) is true. Line 4 is true if (x AND y AND z) is true. The function defined by the table is true if and only if (x AND y AND z) OR (x AND y AND z) = 1. The expressions (x AND y AND z) and (x AND y AND z) are examples of what are called ‘‘minterms.’’ Expressions put together as described are not necessarily the simplest way to express the function. Simplification is somewhere between an art and a science, and will not be discussed here. The example used here simplifies easily. Readers unfamiliar with this aspect of logic may want to stare at the table until they see that one of the variables is irrelevant. Such multiple linear Field GOLEs could produce multiple minterms of an arbitrary logical function of any number of variables. The optical outputs would have to be subjected to an OR operation. That is easily accomplished by directing all of the outputs to a single detector. If light is detected, the OR is true and the truth of the function of many variables is established. This is the reverse of the earlier work in bulk optics by Morozov [1] that was implemented by Guilfoyle [2,3]. In bulk optics, AND is very hard, so they needed to use DeMorgan’s Law (after the logician Augustus DeMorgan 1806–1871) to convert the AND to an OR that is easy for optics. With GOLEs, ANDs are easy too. 3. Bulk and integrated GOLE implementations 3.1. Integrated, non-resonant, photonic switches and modulators In [8], we showed implementation of logic elements with resonant silicon-on-insulator electrooptical switches. The benefit of that approach is that the logic element has an ultra compact area of 100-lm-squared, or less, because of the microring resonator approach. The drawback is that the laser source must be tuned exactly to the resonator

mode, or that the mode wavelength must be shifted or ‘‘trimmed’’ via polymer loading to match the laser wavelength. An alternative approach, non-resonant electrooptical switching in silicon-on-insulator is described in this paper. Here, the spectral range of operation is much wider, and the tuning requirement is more ‘‘forgiving.’’ The tradeoff is that the area of the logic device is, in most realizations, larger than that in the resonant case. The specifics are as follows. The logic device of Fig. 5 can be realized as a compact, monolithically integrated photonic-network-on-a-chip; the prime example of which is a planar waveguide network of electrooptical switches and modulators interconnected by passive rib waveguides. We will assume for the moment that the nominal wavelength of operation is 1550 nm, although the network’s wavelength is definitely extendable to longer-wave regions of the infrared. The switches, modulators, and waveguides (ribs or strips) would typically be realized in silicon-on-insulator (SOI), and the electrooptic (EO) switching mechanism would usually be accumulation or injection or depletion of free carriers (electrons and/or holes). In the filter region between the DLD and DLC, the four 1 · 1 modulators would serve as open or shut apertures (‘‘one’’ or ‘‘zero’’ optical transmission) in the mask plane; that is, individual modulators would be held in a fully on or fully off state. In the text below, we show that it is often convenient to use a modulation structure that is identical to the 1 · 2 switch with one of its two output ports terminated or ‘‘dangling’’. We have identified several integrated-optic 1 · 2 switching components (one of which is new and has not hitherto appeared in print) that are readily interconnected to form Fig. 5 logic device. Our purpose here is to identify non-resonant optical components that can operate over a band of wavelengths whose width is perhaps 5% of the nominal center wavelength. The area or ‘‘footprint’’ of these EO switches is generally an elongated rectangle, hence the length of the rectangle is an issue for the dense packing of logic devices on the silicon chip. However, we shall show that there are recently developed ways to minimize the length of the switch; lengths within the 100–200 lm region. The proposed switches, filter masks, and interconnections are illustrated in the next 12 figures. For simplification of the diagrams, the electrical control paths (two metalized leads extending vertically from each EO switch) are not shown here, but are assumed to be present, and the control signals C1, C2, C2, C1 are assumed to be applied respectively to the first, second, third, and fourth column of four columns of switches. The first switch, Fig. 9, is the Mach-Zehnder interferometer with EO waveguides in each of two arms. This component might have a 1 mm overall length. A technique for reducing the length significantly was reported recently by Wei Jiang and Ray Chen in [21,22]. They combined ‘‘conventional’’ SOI rib waveguides with the line-defect waveguide in a SOI photoniccrystal (PhC) structure as illustrated in Fig. 10. Here the active region is in the mid-region of the PhC lattice where

H. John Caulfield et al. / Optics Communications 271 (2007) 365–376

P and N surface electrodes are placed on either side of the line defect. The dispersion of the PhC is deliberately engineered to reduce the group velocity of light in the line defect, and this produces a significant reduction in the active length needed to give p-radian phase-shift under full electrical bias. Jiang and Chen demonstrated experimentally a 33· reduction. Their active length was 60–90 lm. Hence this MZI 1 · 2 is much shorter than that in Fig. 1. Fig. 11 presents our proposed embodiment of the logic device using the miniaturized MZI’s. The MZI has a cosine-squared switching response with respect to the drive current. Jiang and Chen have also designed an EO MZI that resides entirely within a 2D photonic crystal and this 1 · 2 is quite compact. The EO directional coupler switch is shown in Fig. 12. Here the overall length is perhaps 25% of that in Fig. 9, and the carrier effect can be induced in one arm of the coupler, or within the coupling region. The logic device made from directional couplers is illustrated in Fig. 13. The photonic-crystal directional coupler switch announced recently [23] offers a means to reduce the switching length significantly. This approach is presented in Fig. 14. Here, the carrier control is exerted in the hole-filled silicon coupling zone between the two line-defect waveguides. The switch length is approximately 1/10 of that in Fig. 10, and the PhC implementation would be similar to that in Fig. 12, except that photonic-bandgap lattice would fill the entire. Note that in Figs. 11, 13, 16, and 18, we have chosen to use four 1 · 1 switches (a modulator with the same structure as the 1 · 2 EO component) in the mask region. The 1 · 2 digital optical switch (DOS) is shown in Fig. 15. Here, there is an EO Y-junction with independently addressable EO waveguides in the two arms of the Y-splitter. The advantageous feature is the step-like or saturation-type switching characteristic of the DOS as a function of drive current. A drawback is the length. The splitting angle is typically small; hence the switch length might be 500 lm. Fig. 16 presents the logic layout for an integration of DOSs. We present in Fig. 17 a very compact photonic-crystal EO 1 · 2 switch. In this new device, we use the principle of self-collimated PhC waveguides pioneered at the University of Delaware and at EM Photonics Corporation [24]. By choosing the proper hole diameter and periodicity, the dispersion diagram of the PhC lattice can be engineered to give self-collimating waveguiding at 0 and at 90 optical input angles. The Delaware researchers demonstrated that total-internal-deflection of light at 90 was feasible by etching a deep smooth-walled slot in the SOI, a slot oriented at

Fig. 9. Electrooptic 1 · 2 Mach-Zehnder interferometer (EO MZI).

369

Fig. 10. EO MZI that combines a ‘‘slow light’’ photonic-crystal electrooptically modulated line-defect waveguide region with micro-photonic waveguides.

Fig. 11. EO logic device constructed from a planar integration of Fig. 8 components.

Fig. 12. Shown here is an electro-optically controlled switch – common in integrated optics. But it is easily recognized as a beamsplitter useful in constructing a Mach-Zehnder interferometer.

Fig. 13. Logic device, based on the elecrooptical 1 · 2 directional coupler switch using, for example, perturbation of one coupled arm.

Fig. 14. Photonic-crystal electrooptical 1 · 2 directional coupler switch using EO perturbation of holey coupling region between line defect waveguides.

Fig. 15. 1 · 2 ‘‘digital’’ optical switch using EO perturbation of one or both output waveguides for a step-like switching characteristic.

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C

Beamsplitter

D

Fig. 16. EO logic device constructed from Fig. 7 devices.

F Phase Shifter (P)

E

A

B Fig. 19. An optical Fredkin gates after Shamir et al. 20 years ago are shown here.

P

A

C

B

D

N Fig. 17. Photonic-crystal 1 · 2 switch using self-collimated waveguides, an etched TIR mirror, and a planar, lateral PIN carrier-injector to create a 90 deflection of the input guided beam.

P Fig. 20. This symbolic representation of a Fredkin gate shows both of the relationships between the horizontal lines: pass through and crossover. Which occurs depends on the value of the control setting.

3.2. Bulk optics GOLEs

Fig. 18. EO logic device constructed from Fig. 15 devices.

45 to the beam. We now introduce the concept of lateral PIN injection of electrons and holes to form a lower-index stripe region in the Si PhC lattice, a stripe that will reflect (deflect) the guided light beam by 90 for a sufficiently large index perturbation of the SOI lattice (Dn  103). Fig. 18 presents the miniaturized realization of the logic device, all in one PhC SOI chip, whose area is approximately 100-lm squared. Finally we show the possibility of using multi-modeinterference (MMI) switches, typically in a 2 · 2 configuration that can be employed as a 1 · 2 or 1 · 1, as desired. After further development, there is hope of making the MMI length less than 500 lm, although initial SOI versions have used multi-mode to single-mode waveguide tapers within the EO waveguide region in the center of the device [25] which caused the length to exceed 1 mm. An issue with the MMI is its somewhat narrow (40 nm) wavelength range of operation.

Bulk optics has advantages and disadvantages relative to integrated optics. Its primary advantage is that it is well suited for optical parallelism in 3D space, whereas integrated optics is only parallel in 2D plane in highly uniform planar waveguides, in most cases not parallel and often even the least parallel of all – single transverse mode. Bulk Mach-Zehnder interferometers are relatively easy to make, so there is interest in this approach. On the other hand, integrated optics has advantages in low cost (in production), low voltage, compactness, and ruggedness. On the modern technological level, numerous integrated optical engineering approaches have been developed, such as fiber ribbons or multi-layered waveguides, etc. to solve the problem of parallelism in 2D and 3D. 4. The logic of GOLEs 4.1. Extending GOLEs to fuzzy logic Fuzzy logic [26,27] is an extension of Boolean logic to continuous variables. The term fuzzy logic is very misleading. A longer but more accurate description would be the rigorous logic of fuzzy sets. Many real life sets are fuzzy, e.g. the set of middle aged men. There is no magic femtosecond when a man switches from being young to being middle aged. A 35 year old man may be a little young but more middle aged. It is not noise or imprecision that makes that set fuzzy. It is incurably fuzzy by its nature.

H. John Caulfield et al. / Optics Communications 271 (2007) 365–376

One speaks of the membership of that man in various fuzzy sets and denotes membership values with the symbol l. We allow 0 6 l 6 1. One of the key constraints on fuzzy logic is that it must reduce to the Boolean results when the l values are restricted to 0 and 1. One generalization of the AND function, for instance is that the l of A AND B is the product of their l values. Such generalizations of AND are called fuzzy T-norms. It is easy to verify that the multiplicative T-norm reduces to the Boolean AND when the ls are restricted to 0 or 1. The light positions in a DLD are digital (binary in this case), but the voltages that switch positions are analog. This means that for voltages other than V = 0 and V = V0, light will emerge from both exit ports. Because there are no obvious voltage-dependent loss mechanisms, the total amount of light emerging from the two ports will be conserved. For most modulation schemes, the two outputs will have intensities I 1 ¼ I 0 cos2 ðV =V 0 Þ

ð1Þ

and I 2 ¼ I 0 sin2 ðV =V 0 Þ:

ð2Þ

Here I0 is the incident intensity. We can regard I1/I0 as the membership of V in a class A. Call it lA ðV Þ ¼ I 1 =I 0 :

ð3Þ

Then l:A ðV Þ ¼ 1  lA ðV Þ ¼ I 2 =I 0 :

371

ago [19]. Fig. 19 shows the interferometric version of that device as it would be implemented in bulk optics. In this construction, we have two inputs A, B and two outputs C, D as well as the control P. The system can be aligned so that if P does not change the phase, all of the incident light A will go to C and all of the incident light B will go to D; if P changes the phase of E by p, then beam A goes to D and beam B goes to C. So if we consider A, B (coded by amplitude) and P (coded by un-shift or shift) are three inputs and C, D and P are three outputs, it is virtually a Fredkin gate. We simply use Fig. 20 to express this device. If we cascade four Fredkin gates, we can construct a system of four inputs and four outputs – a different kind of DLD. Fig. 21 shows how this can be done. Again, Shamir et al showed this and other arrangements much earlier [19]. For this construction, the relationship between inputs and outputs can be described in Table 1, where no shifting and p shifting for phase are encoded by 0 and 1 for C0 and C1. For convenience, we simply represent this device as shown in Fig. 22. Note that this kind of a four-input four-output DLD is conservative. So there is no energy lost during the switch. It is obvious that if we just take one input I0, then it is exactly a one-input four-output DLD described above. So this four-input four-output DLD is a generalization of the one-input four-output DLD introduced previously. If we just use the first output O0, we get a typical logic LUT (lookup table) as suggested in Fig. 7.

ð4Þ

Cascading two stages of such systems gives all four terms of the form l ¼ li lj ;

ð5Þ

where i = either A or A and j = either B or B. Under a multiplicative T-norm those are memberships in classes such as A AND B, A AND B, A AND B, and A AND B. This may prove useful in fuzzy control where the fuzzy AND determines the extent to which some rule is applied. 4.2. Extending GOLEs to multiple input signals The GOLEs described so far have begun and ended with a single optical beam. That is an easy way to begin, but not necessarily the place to stop. There follows a discussion of two types of multiple input GOLEs: those with a single output beam and those with multiple output beams. Up to now, we have discussed optical DLDs which can serve as GOLEs. A single incident beam is split to two beams in the first beamsplitter, and they rejoin in the next beamsplitter. However, the second input of the first beamsplitter is not used in this construction. If two beams enter the first beamsplitter, we get a Fredkin gate [28]. This basic concept was described by Shamir et al. two decades

I0

O0

I1

O1 C0

C1

I2

O2

I3

O3 C0

C1

Fig. 21. Allowing crossover between Fredkin gates creates new input/ output arrangements.

Table 1 Look Up Table (LUT) Signal, S

Control, C

1 1 1 1

1 1 1 1

Position 1 p  2 0 0 p 2

Position 2 0 p i 2 p i 2 0

The simple interferometer of Fig. 1 can be so adjusted that the inputs Signal, S and Control, C give the complex amplitudes at Position 1 and Position 2 shown here.

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Table 2 Truth table x

y

z

f(x, y, z)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 1 0 0 0 1

By placing 0 s and 1 s in various places in the last column, we can specify any Boolean function of the three binary variables x, y, and z. This also allows us to implement any such function in terns of AND and OR in a very transparent way.

I0

O0

I1

O1

I2

O2

I3

O3

C0

C1

Fig. 22. This symbolizes the system of Fig. 21 in an easy-to-understand way.

C0

C1

C0

C1

Fig. 23. This is a 4 · 4 extension of the 1 · 1 Do-nothing Machine of Fig. 5.

Furthermore, if we cascade two 4-inputs 4-outputs DLDs with same set of control values, we get another ‘‘do-nothing machine’’ as shown in Fig. 23. 4.3. Cascading GOLEs A GOLE can calculate a value for any Boolean function of any number of variables. All that is required to calculate a function of n variables is to generate 2n paths at the filter plane and then select those paths for which the function evaluates as 1. In practice such devices quickly become huge as n increases. It requires 2n1 interferometers to yield 2n paths, and additional 2n1 interferometers to converge the paths after the filter. Thus a GOLE to compute a function with 32 bit input would require 232 interferometers, more than 4 billion. This is an order of magnitude greater than the number of transistors on current high end microprocessors.

Fig. 24. 2 input OR gate with 4 switches.

It is important to remember that although a 32 bit GOLE would be huge, it would also be a universal gate – able to calculate any 32 bit function. One way to make smaller DLD based gates is to make them more specialized. For example, it is possible to build a DLD OR gate on n inputs using only 2n switches (see Fig. 24). An n input AND gate can be built using only n switches, as there is no need to converge paths. In general, careful construction can drastically reduce the number of switches needed to calculate a specific function. Of course in doing so we lose the universality of larger gates. Electronic logic mitigates this loss by cascading small simple gates to build larger gates. Cascading traditionally involves using the output of one gate as the input of another. By chaining simple gates together, it is possible to model extremely complicated logical structures with a small palette of simple components. We will call chaining gates together in this fashion ‘‘linear cascading’’ to distinguish it from other ways of grouping simple gates together. However, what is important is the ability to model complicated structures with simple devices, something we will call ‘‘modularity’’, not the precise way in which it is accomplished. Linear cascadeability is important in electronic logic only because it achieves modularity. Linear cascading is not readily applicable to DLD based gates (hereafter DLDG) because the input and output are different. A DLDG1 has a single output path that is either on or off. Its inputs are electrical impulses to phase modulators. The closest approximation is what might be called ‘‘transduced cascadeability’’. If we have two DLDGs, J and K, we can use the output of J as an input to K by first using a photoelectric transducer to change the output of J into an electrical signal, and then feeding that signal into a phase modulator in K.2 While achieving the goal of modularity, transduced cascading has drawbacks. Primarily, the transduction step introduces a time delay. Not only does this slow down the overall speed of the logic device, but it also introduces the need for regulation of timing so that detection of the 1

This assumes an interferometric DLD with electronic phase modulators. However the general idea may be applied, mutatis mutandis, to other varieties. 2 Really, the signal will have to be split and fed to two modulators, one on each side of B’s filter plane.

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output of B occurs only after all phase modulators have been activated. If a phase modulator were available that used optical inputs rather than electrical, we could avoid the transduction stage and the time delays it introduces. However, unless the modulation was instantaneous, the system would still be slowed by the latency of the modulators and would thus still require careful regulation of timing. The real advantage of this technique comes when J and K are the same DLD. That is, when the output of J is used to subsequently modulate the phase one of its own interferometers as in Fig. 25. By carefully regulating timing, we can use a single DLD to calculate functions of arbitrary numbers of arguments. For example, let J be a 2 stage DLD as below. Detecting at O will yield the function determined by the filter, a function on 2 arguments. However, if instead of detecting at O we allow O to be used to modulate the phase at A and a, at the same time possibly changing the modulation at B and b and changing the filter, a subsequent well timed detection at O will yield the output of a 3 input function. By letting the cycle repeat more times before detecting the answer, we can compute a function on any number of inputs. While it may not be possible to compute all functions by cycling an n stage DLDG in this way, those functions which can be so computed will realize a huge savings in the number of required switches. The cost for this savings is rigid regulation of timing, a general slowing of calculation, and the need for some method of interrupting the cycle to detect the output of the function. Whether the benefits outweigh the costs will depend on the specific function and application being considered. Another way of achieving modularity depends on treating the output of one DLDG as the reference beam of a second. If the output beam of J is fed into the optical input of K, the output of K can be read as the conjunction of J and K. That is, K will only have a positive output if J has a positive output and K evaluates as 1. If J has an output of 0, then K receives no light. With no light in, K can give no light out. In fact we can chain as many DLDGs together in this fashion as we want. The resulting device

B

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will compute the conjunction of all the DLDGs it comprises. We will call this ‘‘conjunctive cascading’’. Conjunctive cascading becomes important in the light of the Conjunctive Normal Form Theorem which states that any Boolean formula is equivalent to a conjunction of disjunctions. So any function can be calculated by first expressing it in CNF, then calculating the value of each disjunction, and finally calculating the value of the conjunction of the disjunctions. In terms of DLDGs this is accomplished by conjunctively cascading DLDGs which compute the values of the disjunctions. Importantly, an n input OR DLD can be constructed using only n interferometers on each side of the filter, and chaining doesn’t add any interferometers beyond those required to compute the OR. Thus the size of a CNF DLDG grows linearly with the number of arguments in the CNF. Obviously linear growth is a huge advantage over the exponential growth of a GOLE. The advantage is mitigated somewhat by the fact that CNF propositions are not always the most efficient way to express something, but in most cases there should be a substantial savings. As with transduced cascading, further savings can be realized by having J and K be the same DLDG. An apparatus is needed, and easily built, that changes the normal reference beam of the DLDG for its output beam. We simply have an interferometer select either the reference beam or the output of the DLDG as the input (see Fig. 26). This again requires careful attention to timing issues, both with respect to detecting the final output and in ensuring that the DLDG is reset by the time the light has cycled from the output to the input of the DLDG. Such a system will realize a savings in hardware at the possible expense of some slowing of computation. The slowing is due to the likelihood that the light will need to be delayed as it cycles. The merits of this type of cascading will depend on the specifics of the functions being computed. Yet another way of achieving modularity arises from the possibility of building a two output DLDG in which the paths which are normally blocked are instead converged in an alternate output path as in Fig. 27. Such a DLDG will have two output paths, exactly one of which will have light in it. The value of the function is thus encoded both by intensity (whether a specific output path is ON or OFF) and by position (which path is ON). We’ll call such

b Output of System DLDG

IO

A

B

b

a

Reference Beam

Modulation input

Modulation input to A

Transducer

Fig. 25. Transduced linear cascading.

Fig. 26. Cyclic conjunctive cascading.

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O+

I

O-

Fig. 27. DLDG in which the paths which are normally blocked are instead converged in an alternate output path.

a device a ‘‘DLD2’’. One way of building such a device is as a transmissive/reflective GOLE as discussed above. The crucial insight here is that a DLD2 is essentially a switch, light is output on one of two paths depending on the state of the DLD2. Further, a DLD2 is essentially lossless and conservative with respect to the logic it performs. As a result, it is also reversible. But reversible switches are precisely the sort of things we use to build DLDGs. Thus a DLD2 can itself be used as a component in a DLDG. On the left side of the filter plane it can replace any single interferometer, on the right side it is reversed and occupies the mirror position. Rather than chaining gates together, we nest one gate inside another. We call this ‘‘nested cascading’’. Although nested cascading initially may appear quite different than the linear cascading used in electronic logic, it actually accomplishes exactly the same function. That is a basic design for a logic circuit can essentially be ‘‘read off’’ of the expression to be implemented. Suppose, for example, that we wish to calculate IF p, THEN q, ELSE r where p, q, and r are the values of complicated functions rather than simple variables. Instead of building a full DLDG on all the base variables needed and selecting the positive results to re-converge, we can simply use modules that compute the values of p, q, and r arranged in a 2 stage DLD. Specifically, a module for p is placed at A, a q module at the upper B, and an r module at the lower B in the above diagrams.3 Reversed modules are placed at the appropriate places on the right side of the filter plane. If a stock of well designed modules for often needed functions is available, the process of designing complicated logic devices can be greatly expedited in this way. Nested cascading introduces no new issues regarding timing or transduction as it introduces no new components 3 We are assuming that upper paths are positive and lower paths are negative.

or architectures. Its advantages are simplification of logic design with the possibility of a reduction in the required hardware. Whether there is a substantial savings in hardware will depend on the specific case. In the above example, savings will be greater when p, q, and r are more complicated functions and when they share few arguments. When they are not very complicated, or when they share many arguments, this technique may actually yield an increase in the number of interferometers needed. This is because DLD2s require a diverging portion and two converging portions. When a DLD2 is used as a module in a DLD, all of these must be repeated on the right side of the DLDG’s filter plane. This can, of course, be mitigated, at least in part, by the use of transmissive/reflective design. In general, DLD based logic gates increase in size as a linear function of the number of arguments in the function they compute. As with electronic gates, optimization can significantly decrease the total number of components needed. However, the variety of ways of implementing modularity in DLDs promises substantial saving in components even when the functions are not fully optimized. This combined with the faster throughput of DLDs as compared to fully electronic gates should yield a huge savings in computation time for a given function. 4.4. Flynn classification and beyond for field GOLEs In scalable parallel computers, one of the most fundamental issues is the basic model of parallel execution. Flynn’s characterizations involve Instruction, I, and data, D. A Turing machine is a SISD (Single Instruction, Single Data) system [29]. At any moment, the machine has a Single Instruction (operation to perform) on single piece of data. There is no concurrency. MISD makes no sense, except possibly in the context of quantum parallelism – a topic not discussed here. MISD says the processor functionality changes while a single set of data are being processed. SIMD is very powerful, however. It includes all forms of concurrency now used – parallel, pipelines, systolic, etc. The most powerful, of course, is MIMD. Unfortunately, there is almost no work on MIMD, because it is too complicated and the motivation to use it has not been widespread. GOLEs introduce a new kind of instruction – FI (Flexible Instruction). The processor can do different things under different circumstances. The Field GOLE example we showed earlier is a conventional SIMD system – all of the GOLEs are following the Single Instruction: ‘‘be an AND gate.’’ We could, however, let different ones do different things, to make an MIMD. To make a FIMD system, we would allow the functionality of each GOLE to change (most likely depending on its or other GOLEs’ earlier results). Clearly, just as a Field GOLE is the most flexible and powerful logical system that has been so far conceived, the FIMD application of the Field GOLE is the most powerful member of the extended Flynn hierarchy.

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5. The practical potential of GOLEs 5.1. Applications of GOLEs The most obvious applications of GOLEs are those on which multiple phase-modulated optical bit streams already exist and one wishes to perform logic on them free of cost in bandwidth and energy consumption. One might think of PONs (Passive Optical Networks) that could be self-referentially adaptive or optical packet switching where we seek to match the header perfectly with a fixed address code. 5.2. Limitations of GOLEs GOLEs have some limitations that accompany the advantages we have just described. For example, the input arguments in the simple cases we have illustrated have been electrical, not optical. But if we have two streams of data on mutually coherent beams of light – one phase modulated and the other unmodulated, then indeed we can use one beam of light to control the other. Other than optical logic, the only other motivation for transmitting a mutually coherent reference beam along with the signal beam has been quantum encryption [30]. We have recently suggested many ways to accomplish such transmission over long distances through single-mode fibers or free space [31]. The discussion above describes numerous ways to implement GOLEs and each of them has numerous variations. Thus we have not done detailed signal to noise, bit-errorrate and other analyses on any particular version. We plan to build a GOLE in the near future and provide that analysis for the particular version built.

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which interferometry does the switching. Second. The invention and development of DLDs took place several decades ago, so many readers may be learning about them for the first time here. There is a variety of ways to scan or deflect light. The most popular ones are mechanical (tilting mirrors, tuning forks, and the like) and acoustooptic. The former are too slow for some applications and the latter are too inefficient and power consuming for other applications. This drove researchers to seek electrooptic deflectors as a possible way to achieve high speed and high light efficiency. Electrooptically tunable prisms were unsuitable, because they could not produce very many resolvable spots. Roughly, the number of resolvable spots S is related to the length L of such a prism by S ¼ ðL=kÞDn; where Dn is the maximum index of refraction change that can be induced and k is the wavelength. It is very difficult to find materials that allow Dn much bigger than 103, so we need very large (L/k). For green light (k = 0.5 · 104 cm) and a one cm deflector, we have (L/k) = 2 · 104. At Dn = 103, this would allow about 20 spots – too few for most applications. Thus there was a need to develop new, innovative means to deflect light electrooptically. The idea of the DLD is to simplify the task by building up a large number of resolvable spots from many two-spot deflectors. The two-spot deflector could be either an analog prism as just described or a switch determining which of two paths light would take. The latter approach proved more attractive. For instance, Wollaston prisms of fixed width but variable length could be made to deflect light at angles, ±h, ±2h, ±4h . . . N stages could then put light into one of 2N positions. Of course, that requires 2N  1 switch-deflector pairs.

6. Conclusion Appendix B. Supplementary data Generalized optical logic elements (GOLEs) can be implemented in numerous ways in both integrated and bulk format. Our descriptions have emphasized their use with silicon photonics for two reasons: the rapid and ongoing development of that field and its obvious convenience. GOLEs themselves can be generalized in many ways (Fuzzy GOLEs, Field GOLEs, Fredkin GOLEs, and Generalized Fredkin GOLEs). They appear to constitute a rich field for development and exploitation. Acknowledgements The work at Fisk University and Idaho State University was done under Contract No. HQ00604C0010 for the United States Missile Defense Agency. Appendix A. An introduction to digital light deflectors (DLDs) This appendix seems necessary for two reasons. First, GOLEs are based on DLDs, albeit very special ones in

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