which is in a good agreement of the predictions of the analysis performed.
caused by the resistance mismatch is as follows:
ER(%) =
E
~(7) 2(: ARj "IN IO0 '
It is possible to achievc very accurate resistor ratios [2, 6, 71. There resistors consist of several fingers connected at their ends using lowresistivity metal. This stmchlre might result in 0.1% matching accuracy if the finger widths are relatively wide (e.g. 10 pm in a 0.8 pm technology). For considered error less than 0.2%, with matching accuracy AR/R=0.5% and for the input voltage V , ~ = 0 . 5V it is necessary to have (21~~/Ko20)'~2>0.31 V, which is not a difficult requirement.
Conclusion: A CMOS transconductor based on the bisection of the input voltage using a ncw type of current canvcyor has heen discusscd. The transistor dcterinining the transconductance does not carry bias current. The transconductance is current-controllcd, and independent of the threshold voltages o f the devices used. It shows wide bandwidth, a goad linearity. and B &1.5 V operation.
0 IEE 2003 Eiectro,lic.s L ~ I I W S oniitrr NC 2003n024 DOI: 10.1n49/~1;~uu3au24
I October 2002
N. TadiC (Depar.rmmt Electrical Engineering. University of Montenegro, Cetinjski put hb, 81000 Podgorica, Montenegro. Yug"s1""ia) E-mail:
[email protected]
D. Gabovie (West Virginiu Stole Community and Teclinical College, Cunipirs Bot 183, Inrtittite, WY 25112-1000, USA) E-mail:
[email protected]\,sc.edu References DUPUIE. s T., and ISMAIL, hl.: 'High frequency CMOS tmnsconductors' in TOUMAZOU. C.. LIDGEY, F.J.. and IIAIGH, D.C. (Edr.): 'Analogue IC design:
input voltage, mV Fig. 2 Output cirrrent agoinst iqmt voltage *,ill, cowesponding linearity ellvrs
35-1 10
To3
1n5
107
io8
the cunmt-mode approach' (Peter Peregrinus Ltd., Stevenage, 1990). Chap. 5 JOHNS. D., and MARTIN, K.: 'Analog integrated circuit design' (John Wiley & Sons, New York, 1997) TSIVIIXS, Y.P.: 'Operating modeling of the MOS transistor' (McGrawHill. New York, 1999) T m l t . N., and conovlc. D.: 'A voltagc-controlled resistor in CMOS technology using bisection of the voltage range', IEEE Trons. Instrum. M ~ ~2001, ~ . su, . pp. 1704-1710 FERRI, G., and GUERRINI, N.: 'High-valued passive element simulation using low-voltage low-power current conveyors for fully integrated applications', ]E,?€ Trans. CircuiI.s Syst.. 11: Ano10.g Digit. Signal P ~ ~2nn1. ~ 48,~ pp.~ 405409 ~ . . O'LEARY, P.: 'Practical aspccts of mixed analogue digital design' in sow, R s.. MALURERTI. F.. and FRANCA, I. (Eds.): 'Analogue-digital ASICs, circuit techniques, design tools, and applications' (Peter Peregnnus Ltd., Stevenage, 1991) MALOBERTI, F.: 'Layout o f analog mixed analog-digital Circuits' in FRANCA. I.. and TSIYIDIS. Y. (Eds.): 'Design of analog-digital \'LSI circuits for telecommunicalion and signal processing' (Pmnrice Hall. Englewood Cliffs, NJ, 1994)
frequency, Hz
Fig. 3 F~eququencycharucterisrics OJ tronsconductnnce 0 IC= 18 PA 0 I c = Z S pA V &32 PA 0 0 v I~.Qn"T)/lV,h., - V")
General design method for complementary pass transistor logic circuits
Simulation resu1t.r The operation of the transconductor shown in Fig. 1 has been simulated using SPICE with a l e w l 3 MOS transistor model for AMlS ABN n-well CMOS process with I.5 pm feature size ( i = O . 8 pm) obtained by MOSIS. The aspccl ratios of the MOSFETs used are follows: 4.8 p m / l . h p m (M2,), 9.6 "11.6 pm (MI), 27.2 k " 1 . 6 pm W - M , , MI,, M W M , d , 32 pm11.6 pm (Mz M,, Mg-M,,, MII-M,,, M,,,; Mx. M d and 240 vmI1.6 pm (MI,). Resistors R = 5 kR, Rain = I O kR (inserted between the nodes Z of TOCCs), currcnt source I n = 5 0 pA, and supply voltages of f1.5 V have been used. DC transfer characteristics with corresponding linearity errors for different values of the control current IC are shown in Fig. 2. One of the inputs has been grounded, V,,,=O. The input voltage V,,= VINI has been swept from -0.5 to 0.5 V The worst-case linearity error is 4 . 8 % . The frequency characteristics of the transconductance with the same values of the control current IC as in the case of the DC response are shown in Fig. 3. The 5% frequency bandwidth is found to he 97MHz. Simulation of the resistors mismatch influcnce has also been performed. For matching accuracy AR/R=0.5% (resistances used: 5.025 and 5 kR), and for the same conditions mentioned above, the worst-case linearity error is still ,.A pulse generator (PC) provides hvo negative pulses at these rising edgcs. The phase error can he obtained by comparing the output of two
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