Materials Science and Engineering B101 (2003) 313 /317 www.elsevier.com/locate/mseb
Electrical barrier properties of meso-porous silicon B. Remaki *, C. Populaire, V. Lysenko, D. Barbier Laboratoire de Physique de la Matie`re (UMR CNRS-INSAL 5511), INSA de Lyon, Bat. 502, Avenue A. Einstein, F-69621 Villeurbanne cedex, France
Abstract We present a contribution dealing with the study of the barrier properties of meso-porous silicon (PS) with metals and p -Si crystalline silicon. Metal/PS/p -Si and p -Si/PS/p -Si structures with different thickness (1 /10 mm) of PS are investigated by means of current /voltage and capacitance /voltage characteristics combined with thermal stimulation in the 150 /350 K temperature range. These experiments allowed a clear separation of bulk and contacts contributions to the electrical impedance. The barrier properties (nature and heights) of metal/PS contacts and PS/Si interfaces are then evaluated. The p -Si/PS/ p -Si structures exhibit ohmic contacts allowing space charge limited current (SCLC) ensured by carriers injection in the PS layers. From this analysis, the electrical behavior of the metal/PS/p -Si structures is interpreted in terms of a Schottky barrier biased through a semi-insulating PS layer. # 2003 Elsevier Science B.V. All rights reserved. Keywords: Porous silicon; Electrical characterization; Electronics transport
1. Introduction Porous silicon (PS) is considered as a promising material with attractive potentialities for electronic and sensor devices. Since the discovery of its luminescence properties [1], there has been a rapid growth in studies of this material. Nano-porous form (crystallites size around 1/3 nm) was widely studied particularly in the hope of silicon based photo-emitting devices production [1 /4]. However, in recent years, studies are devoted to other applications [5] such as active layers for chemical sensors, insulating substrates for passive optical devices and thermal microsensors [6 /8]. For most of these applications meso-PS (pores size around 10 nm) which is obtained from p monocrystalline substrates is more adapted. So, a detailed study of the electrical transport in this material is of a great technological and scientific interest. Meso-PS morphology presents columnar structure without quantum confinement. It is known as an electrical semi-insulator even at low porosity [9,10]. Various mechanisms explaining the insulating properties were suggested such as the free carriers trapping by the
* Corresponding author. Tel.: /33-472-438-327. E-mail address:
[email protected] (B. Remaki).
states of a large specific surface. Besides, rectification and carriers injection properties are reported in works based on current /voltage investigations of metal/thin PS layers contacts [11 /14]. However, these effects are not clearly related to the existence of a Schottky barrier and the injection mechanisms remain ambiguous. In particular, when a rectifying contact is assumed, the analysis of the space charge region is disturbed by the semi-insulating bulk impedance. This work is a contribution to an accurate determination of the barrier properties of meso-PS with metals and p silicon.
2. Experimental Meso-porous layers were formed by means of wellknown anodic dissolution process that is usually achieved in HF-based electrolytes. In this work, monocrystalline (100)-oriented highly doped p-type Si wafers with resulting electrical resistivity of about 0.02 V cm and a standard electrochemical cell with metallic back-side electrode were used. Due to the enhanced wafer doping concentration, ohmic contacts to the backside of the wafer were not necessary. PS circular zones with area of 1 cm2 were fabricated in a solution of HF (50%) and ethanol (HF(50%): ethanol/2:1) at a 75 mA cm 2 anodization current density values to ensure
0921-5107/03/$ - see front matter # 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0921-5107(02)00731-6
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around 50% porosity values of the porous samples. The thickness (in range of 1 /10 mm) was controlled by the exposure time to the etching process. After fabrication, the wafers were rinsed in de-ionized water. Then, Au/ porous-Si/p -Si structures were fabricated using a vacuum thermal evaporation of gold electrodes. The metallization is made through a mask that defines 2 mm diameter circular electrodes. In order to realize the pSi/PS/p-Si structures, p poly-silicon layers with thickness of 0.5 mm are formed on a part of the samples before the metal deposition step. Standard low pressure chemical vacuum deposition (LPCVD) at 620 8C and 450 mTorr is used. Boron implantation is realized with a high dose (/1015 cm 2) followed by a 900 8C annealing treatment. Poly-Si/PS/p-Si samples of 10 mm2 area are then cut out of the wafers. The details of the geometrical structure are given in Fig. 1. The complex impedance and DC currents I /V measurements were performed in a primary vacuum, at a controlled temperature. The complex impedance analysis was made in parallel mode using a HP 192 bridge. The DC current characteristics were obtained from a HP 441 pico-amperemeter using a sufficiently slow ramp voltage to avoid non-equilibrium regimes.
3. Results and discussion 3.1. p Poly-Si/PS/p -Si structures Fig. 2a shows typical current density/voltage characteristics for p-Si/PS/p-Si structures with PS layer of different thickness (1 /10 mm). The curves are symmetrical and weakly dependent with the temperature as indicated in Fig. 2b. An ohmic behavior is observed at low electrical field (B/100 V cm 1). At higher electrical field (up to 104 V cm 1) the conductivity increases with the voltage and the characteristics become surlinear. The logarithmic representation of the current
density J versus the thickness e in Fig. 2c exhibits a straight behavior with a slope mean value of /2.8. Such value (not far from the ideal value of /3) indicates that space charge limited currents (SCLC) currents are prevailing. The current density J is then related to the voltage V using the Child equation [15]: J s : e 1 : V o : mD : e 3 : V 2 s : e 1 : V mD : Cg : e 2 : V 2
(1)
where s is the intrinsic conductivity, o the dielectric constant and mD the effective drift mobility. Cg is the geometrical capacitance (per unit area). The capacitance of p-Si/PS/p -Si structures is not frequency nor voltage dependent as shown in Fig. 3c. So, Cg is directly measured using a HP 192 complex impedance bridge in parallel mode. These characteristics indicate that PS form an ohmic junction with p-Si (substrate and poly-silicon gate). According to the equivalent circuit in Fig. 2d, the current through the p-Si/PS/p -Si structures is controlled mainly by the bulk PS layer impedance and injected carriers. The intrinsic conductivity s, calculated from the linear part of the J /V curves, is in 0.1 /1 mS cm 1 range. It is 8/9 orders of magnitude lower than the initial substrate conductivity (around 102 S cm 1). This strong decrease of the electrical conductivity is widely reported and generally attributed to the free carriers trapping by the surface states. From the Child equation Eq. (1), the effective drift mobility is found around 1 cm2 V 1 s 1. This value is 2/4 orders of magnitude larger than those reported in the best cases for nano and meso-PS [16]. This indicates that the injected carriers are relatively free carriers. Such unexpected high values of the mobility could be related to better experimental conditions using symmetrical p-Si/ PS/p -Si samples. Indeed, the measurements are not affected by current injection through a Schottky barrier. Besides, the mobility could be enhanced by the annealing heat treatment following the ionic implantation step.
Fig. 1. Geometrical configuration of the samples: (a) poly-Si/PS/p -Si structures; (b) Au/PS/p -Si structures; PS layers are in 1 /10 mm range.
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Fig. 2. Current density /voltage characteristics of p -Si/PS/p -Si structures: (a) at different thicknesses; (b) at different temperatures; (c) corresponding logarithmic representation of the current density vs. the thickness indicating SCLC regime; (d) associated impedance model.
Furthermore, we have observed the same electrical behavior in other disordered materials such as molecular semiconductors [17]. Finally, as it will be shown below, this preliminary study is an interesting basis for the interpretation of the electrical transport phenomena in metal/PS junctions. 3.2. Au/PS/p -Si structures Current density/voltage characteristics of Au/PS/p Si samples are shown in Fig. 3a. Under vacuum, a rectifying effect is observed for different thickness (2 /10 mm). Capacitance measurements confirm this behavior. As shown in Fig. 3c, for the most conductive samples, the measured capacitance is much higher than the geometrical value and exhibit a voltage and frequency dependence. This could be related to a space charge region corresponding to a Schottky barrier in series with
the PS layer impedance. Furthermore, the J /V curves are found strongly dependent on the temperature as shown in Fig. 3b. The corresponding barrier height deduced from the Arrhenius diagrams of the reverse current is typically 160 meV. Assuming an ohmic contact at the p-Si substrate side as suggested by the previous study, these results indicate that metal/PS junctions are Schottky-type with a strong dependence on the environmental conditions. For most of the samples, the current decreases in presence of ambient air. This phenomena is no unexpected because oxygen and humidity are known as electrically active species in PS. The corresponding electronic mechanisms are not clearly identified but we think that a part of the current decrease could be attributed to the presence of carriers traps generated by the association of oxygen and silicon or surface defects. However, an accurate investigation of this effect (which is not the aim of this paper) could be
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Fig. 3. Electrical characteristics of Au/PS/p -Si structures: (a) typical current density /voltage characteristics for different thickness of porous layer in ambient air and vacuum; (b) typical J /V curves at different temperatures; (c) C /V characteristics showing a strong frequency and voltage dependence in comparison with p -Si/PS/p -Si samples; (d) schematic electrical model.
complicated by its poor reversibility. In any case, it is obvious that atmospheric ambiance and/or high temperatures could mask the rectifying effect. Consequently, according to the schematic model proposed in Fig. 3d, the current is controlled by the depletion region at the Schottky barrier biased through the PS layer impedance. At low values of the intrinsic conductivity (B/0.1 mS cm 1), the impedance of the samples is controlled by the PS layer giving symmetrical J /V characteristics (sample in ambient air in Fig. 3a). For relatively high values ( /1 mS cm 1) of the intrinsic conductivity of the PS layers, the impedance of the sample is controlled by the Schottky barrier. In these last conditions, the depletion region capacitance is directly measured at low frequencies. Fig. 4 shows a C /V dependence of an Au/PS/p-Si structure carried out at 1 kHz, under vacuum. The space charge density and the barrier height can be extracted from the corresponding standard 1/C2 versus V characteristics [18]. Our measurements give a barrier height value of
130 meV, close to those obtained previously from Arrhenius diagrams. The space charge density value is 1.8 /1017 cm 3 in the 20 /40 nm prospected zone. This value is several orders higher than the free carrier density of 1012 /1013 cm 3 calculated from the intrinsic conductivity and drift mobility for p-Si/PS/p -Si samples. This could be considered as a direct evidence of a high concentration of carriers traps in PS.
4. Conclusions Meso-PS contacts with p-Si and gold are investigated by means of the current /voltage and capacitance /voltage methods. Using quasi symmetrical p -poly-silicon/PS/p -Si samples, we have shown that meso-PS form an ohmic contact with its p-Si substrate. This permits us an accurate interpretation of the Au/PS/p -Si structure’s characteristics. The rectifying behavior is clearly related to the existence of a Schottky
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Fig. 4. C /V characteristics of Au/PS/p -Si structure at 1 kHz with PS layer thickness of 10.4 mm (m). Corresponding standard 1/C2 vs. V curve (X ).
barrier. Its low energetic height could explain the relatively poor rectifying factor of these junctions. The corresponding space charge density in the depleted region is several orders higher than the intrinsic free carrier’s concentration in the porous layers. This confirms the existence of a high concentration of carriers traps in PS. However, the strong dependence of the electrical behavior on the environmental conditions indicates a complex nature of the electronic transport. We think that further investigations, on structures such as symmetrical p -Si/PS/p -Si junctions could provide interesting data.
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