Complex Cascaded Bandpass Σ∆ ADC Design Nithin Kumar Y.B., Selc¸uk Talay, Franco Maloberti Electronic Department, University of Pavia 27100, Pavia, Italy Email:
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Abstract— The design of a quadrature bandpass Sigma-Delta (Σ∆) ADC build by cascading two complex modulator is presented. The utilization of cascading enables the independent control of zeros of the noise transfer function. Design method and simulation results including errors due to non-idealities as well as limits of a fourth order scheme are presented. The flexibility of placing notches at critical frequency and benefits are outlined.
I. I NTRODUCTION An important block of communication systems is the A/D converter (ADC) of the receiver architecture. Today’s solutions, especially for mobile applications, require very high operation speeds and high resolution for meeting the architecture requirements [1], [2]. The downconversion to near baseband frequencies is preferred to base-band downconversion because for low-IF, where signal is downconverted to low or mid frequency range, hence, the 1/f noise and DC offset effects significantly decrease. The type of ADC preferred in such systems is often a band-pass (Σ∆) ADC [3] with discrete or continuous-time scheme. Operation in intermediate frequencies reduces the complexity of ADC design considerably. However, the bandwidth requirements for inner blocks increase compared with the direct conversion approach. One solution to this drawback is to use complex [4] ADC design where the bandwidth of the ADC covers only the band of interest. Since the bandwidth is shifted to positive frequencies, the bandwidth requirements for ADC is reduced, hence implementation is easier and advantageous. This work describes an ADC structure taking the benefits of not only complex ADC design but also realization in a cascaded style namely Complex Cascaded Sigma-Delta, which is flexible and can be utilized in applications with various stringent specifications. Although the presented idea can also be implemented in single-loop scheme, cascading allows designer benefit from independent NTF zero placement for each block. Hence, overall system design is easier to design and simple building blocks result with facilitated implementation where many realization options are available. The following sections introduces complex cascaded SigmaDelta ADC’s. The latter section introduces architecture and then focused on non-linearity performance of the structure. Last section concludes the presented work.
gain coefficients achieve a complex transfer function. Hence the filtering can be performed non-symmetrically, focusing on positive frequencies and pay less attention to negative frequencies where image frequencies lie. Hence complex NTF with a set of zeros on the unity circle at the positions ejφi , i = 1, n can be achieved as analytical definition is Pn ¸ n · Y a1 ej i φi ejφi =1+ + ··· + (1) NTF = 1− z z zn 1 The method developed in this P paper limits the zero pon sitioning to situations for which i φi = 0, π/2, π, 3π/2 or correspondingly the last coefficient of (1) is 1, j, −1 or −j. The reason of the choice is totally from implementation perspective. This work utilizes n = 2 and delay elements “z −2 ” are enough for implementation and basic building block with complex transfer function z −1 /(1 ± jz −2 ) can be achieved. The design method discussed in [5] gives rise to the basic modulator used here in this cascade scheme. It is shown that a simple two delay scheme realizes two terms of the expected NTF; therefore, it is necessary to realize the inner term of the equation (1). Then NTF
= 1 − (ejφ1 + ejφ2 )z −1 − jz −2 = 1 − αz −1 − jz −2
(2)
√ where α is a complex number whose module is less than 2. The missing term to be synthesized is −αz −1 . If the phases of the zeros are symmetrical with respect to 3π/4 (φ1,2 = 3π/4 ± δ), then √ (3) α = −(1 + j)k, (k < 2) Notice√that if k = 1, then z1 = 1 and z2 = −j. Moreover, for k = 2 the zeros are coincident.
II. C OMPLEX C ASCADED S IGMA -D ELTA M ODULATORS Complex Sigma-Delta Modulators are gaining more and more interest in the last few years [2], [4]. The approach is to cross couple the I and Q channels with branches whose
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Fig. 1.
Block diagram for for realizing N T F = (1 − αz −1 − jz −2 ).
quantization noise of the I and Q paths of the first modulator and obtain a complex output OU T = OU Tr + j · OU Ti OU T = Xz −4 + ε2 (N T F1 )(N T F2 )
(4)
where ε2 = ε2,r + j · ε2,i . The complex noise transfer functions of the cascaded solution are the second order complex expression and can take any of the form
Fig. 2.
1 + z −1 k(1 − j) − jz −2 1 − z −1 k(1 + j) + jz −2 1 − z −1 k(1 − j) + z −2
Block diagram for realizing N T F = (1 − αz −1 − z −2 )
1 − z −1 k(1 + j) − z −2
The implementation of the missing term requires one delay and two quantization noise components (εR , εI ) one from the real path, the other from the imaginary one. This is done with the diagram of Fig. 1: the two delay are separated into single delays, while the addition of the two quantization errors amplified by k is injected into the intermediate point with appropriate sign. Notice that the proper change of the signs used in Fig. 1 obtains NTF of the form (1 − αz −1 + jz −2 ) while schemes of the type indicated in Fig. 2, or an equivalent one with modified signs, realizes NTF of the type (1 − αz −1 ± z −2 ). A simple topological modification transform the architecture of Fig. 1 into the one of Fig. 2; moreover, changing signs is straightforward. Therefore, assuming to use the same value of k, it is easy to foresee a possible digital re-configurability of the complex modulator. With the above described method it is possible to obtain two complex zeros in the NTF. The method can be extended to higher order or, better, the modulators of a MASH type architecture. A. Cascaded Sigma-Delta Modulator Cascaded or MASH architectures are preferred especially in Sigma-Delta ADC’s due to their structure immune to instability. Hence cascading stable structures result in a stable cascaded structure where increased order satisfies the desired specifications. Obviously, cascading modulators must account for the loading and the accuracy of the signal transfered from one block to another. Figure 3 shows the cascade of two blocks whose noise transfer functions N T F1 and N T F2 , are possibly different. The conventional processing used for MASH schemes cancels the
Fig. 3.
Block diagram of MASH.
(5)
therefore, different combinations are possible to fulfill the desired specifications. Notice that the NTF of (5) give rise to zeros that are symmetrical with respect to dc, fN /4, fN /2, 3fN /4 and fN or the negative counterparts. Therefore, the designer can decide for a proper placement of pair of zeros that met the specifications and minimize the limits possibly caused by components’ mismatch. B. Image related performance degradations Image in communication systems is one of the major concerns because it is the main cause of poor performance. If the I and Q signals handled by a quadrature system are not matched perfectly the desired performance deteriorate because mismatch between paths produces a spur image [6]. Furthermore the limit causes a leakage of the quantization noise near the image frequencies to the signal band [7]. The errors, due to the ADC non-idealities, are corrected by exploiting the feature of the ADC architecture. Since the complex zeros of the cascaded structure can be easily placed at any point in the unity circle by changing the values of a capacitor pairs that determine the coefficient “k”, the design can foresee placement of zeros of the NTF at critical complex frequencies for obtaining image suppression. For example, it is possible to place a zero directly at the expected image frequency. Another strategy is to have the zero near the image frequency for benefiting from a good image suppression even with a relatively high signal bandwidth. III. C ASCADE A RCHITECTURES The design method describes in the previous section enables achieving different kind of complex responses. For this we can, for example, cascade two complex modulators implementing the same or different types of the NTFs indicated in (5). For a quasi zero IF we can combine pair of zeros symmetrical respect to fN /4 and complex zeros symmetrical with respect to zero. For IF close to fN /2 we can use the one that gives complex zeros symmetrical with respect to that complex frequency as second architecture and so forth. The relative placement of zeros and the resolution of the quantizer are determined by the used OSR, the required SNR and the image suppression requests. For maximizing the SNR the zeros must
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TABLE I Parameter Bandwith SNR IF
Value 2.6 MHz 60dB 0.75MHz / 1.25MHz / 4.5 MHz
be equally spaced on the unity circle. As a result, even if the method does not give a complete freedom to the NTF zero placement, the design flexibility is sufficient especially for a low OSR. Consider for example the specifications of Table I that foresees a moderate SNR but requires a digitally programmable IF at three defined values. The use of a sampling frequency equal to 10 MHz and a 3-bit quantizer achieves the specifications. The first IF is lower than fN /4 and two zeros obtained with the first NTF indicated in (5) ensure noise shaping in the high frequency range, while two zeros symmetrical with respect to dc obtain the shaping at positive and negative frequencies around zero. The result is shown in Fig. 4. Since the second IF equals fN /4 the use of two modulators of the same type that obtain the first NTF of equations (5) but with different value of k realize pairs of zeros that embrace the IF as shown in Fig. 5. The spectrum shows that one of the zeros is at dc for an optimum suppression of noise in the vicinity of image which may fold in the band of interest [7]. The third IF is obtained by cascading two modulators with NTF corresponding to the second and third equation (5). Two zeros are symmetrical with respect to 3fN /4 to provide the shaping at frequencies lower than the IF and two zeros are symmetrical with respect to fN for the high frequency shaping. In summary, the requirements are properly satisfied and with digital programmability that requires to change interconnections, signs and in one case the value of k. This is not difficult to obtain because with switched capacitor implementations the value of k is set by the value of a pair of capacitors. IV. N ON - IDEALITIES AND S TRUCTURE P ERFORMANCE The circuit implementation of the proposed quadrature structures is sensitive to mismatches. Hence their effect on performance should be analyzed. The mismatch has different impact depending on whether the modulator realizes −j, +j, −1
Fig. 5.
PSD of the architecture with IF=1.25MHz
Fig. 6.
PSD of the architecture with IF=4.5MHz
or +1. Namely, if the network has cross-coupling with negative loop, systematic errors caused by a static mismatch are almost suppressed and the limit is not crucial. Therefore, since the quantization error of the first modulator used in the cascade is cancelled in the digital domain using the expected NTF it is advisable to use the modulator with minimum sensitivity first. The first and the last terms of the NTF depends on the two delays and the second term is controlled by capacitor ratios. Therefore, possible limitations of the op-amp used can cause a leakage in the z −2 term while capacitor mismatches affect the accuracy of the complex zeros placement. The limit caused by the op-amp is normally negligible and can be made small by using more power that increases the bandwidth or with suitable architectures that provide high gain. An error on k causes a shift of the zeros, that until a given error remain inside the unity circle, proportional to the sensitivity of φ1,2 to k. If the zeros are apart enough the sensitivity is low and the effect of mismatches causes a negligible variation of the SNR. The above point is verified with analytical study. By inspection of Figure 1, accounting for possible errors it results YR
= (XR + YI − PI )z −2 + k · ε1 z −1 + εR
YI
= (XI − YR + PR )z −2 + k · ε2 z −1 + εI
PR ε1,2
(6)
= YR − εR ; PI = YI − εI = εR (1 + δ1,2 ) + εI
that gives the extra terms kδR (εR + εI ) + k(δ1 εR + δ1 εI ) Fig. 4.
PSD of the architecture with IF=0.75MHz
kδI (εR + εI ) + k(δ2 εR − δ2 εI )
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(7)
The left part of the extra terms moves the zeros from their original position. However, for expected mismatch in the order of 0.1 − 0.4%, the deviation from the nominal placement is limited. The remaining part causes a leakage that gives rise to a slight increase of the noise in the signal band. Behavioral simulations show that the degradation of performances is well acceptable with the level of mismatches obtained in real implementations. The only critical problem is that the shift of zeros in the first modulator of the cascade changes the N T F with respect to the expected value, N T Fid , used in the digital cancellation block. The limit causes a leakage of the quantization error of the first modulator by (N T Fr −N T Fid ). Therefore, depending on the architecture, it is advisable to use as first modulator the one that has the lower sensitivity to the value mismatch. Simulation results show that the architecture with IF=1.25MHz, the SNR is not significantly affected for a mismatch in the k factor as large as 0.5%. For larger mismatches the loss in the SNR becomes significant and is 3 dB for a 1.5% mismatch. This result is for inner zeros produced by the second modulator. For the reverse condition the situation is worst and the loss at 1.5% mismatch becomes 6 dB. The results are summarized in Fig. 7 and also the PSD of the structure with an exaggerated mismatch error as much as 2% is provided in Fig. 8.
Fig. 7.
it is desirable to have performance evaluation for SNR vs BW. Fig. 9 shows the SNR vs BW of the 2-2 MASH architecture. It is evident from the figure, high SNR is achievable at the center of the noise shaping curve and then SNR remains almost constant in subsequent regions of the bandwidth, finally decreases exponentially in out off noise shaping region. Hence, there is a region where the bandwidth may vary due to the non-idealities but the SNR stays at same level.
Fig. 9.
BW vs SNR for second order system
V. C ONCLUSION In this work a cascaded complex Sigma-Delta ADC structure is presented. Many design examples for same specifications show that the structure can be adapted to various different applications. Also, non-linearity issues were examined especially major error source in quadrature systems; the mismatch error and sensitivity. ACKNOWLEDGMENT This paper has been supported by the Italian Ministry of University and Education MUR-Firb, contract RBAP06L4S5. Also authors acknowledge Prof. Amit Patra, Department of Electrical Engineering, Prof. N.B. Chakrabarti, AVD Lab. both are from IIT Kharagpur and Edoardo Bonizzoni from IMS Lab. for their technical contribution to this work.
SNR of structure with mismatch on k1 (aps1) and k2 (aps2)
R EFERENCES
Fig. 8.
PSD with 2% mismatch and ideal response
A. Bandwidth versus SNR performance In some of the receiver applications SNR requirement varies with bandwidth of the signal. SNR performance entirely depends on the noise shaping property of the system. High SNR can be achieved in the bandwidth near to zero locations. Hence
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