Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 6, JUNE 1987

Comparison of Experimental and Computed Results on Arsenic- and Pholsphorus-Doped Polysilicon Emitter B polar .Transistors PETER ASHBURN,DAVID

J. ROULSTON,

AND

C . R. SELVAKUMAR

Abstract-This paper presents a detailed comparison of the measemiconductor tunnel devices. The second type of model sured and computed electrical characteristics of polysilicon emitter biexplains the improvedgains in terms of the transport polar transistors over a wide range of processing conditions. Lletailed properties of the polysilicon. Ning and Isaac [2] showed electrical measurements are made of both the emitter resistance and the base and collector current as a function of base-emitter ~oltage. that a factor of approximately three improvement in gain Devices with arsenic- and phosphorus-doped emitters are considered, was obtained when the emitter was contacted via a polyas well as both with and without a deliberately grown interfacial oxidesilicon layer, and this was explained by a lower mobility layer.Thetheoreticalcharacteristicsarecomputedusinga unified in the polysilicon. Other authors [6], [7] have refined this model that incorporates both transport and tunneling mechanisms. It model and incorporated more detailed descriptions of the is shown that the measured emitter resistances across a ,wide range of processing conditions canbe satisfactorily explained using a tmmeling polysilicon structure. More recently, Neugroschel et al. model with a single value for the electron effective barrierheig:ht (0.4 [8] have suggestedthat the transport properties vary across eV). Values for the modeling parameters are obtained, in sowe cases the polysilicon, with the gain being controlled bya highly uniquely by measurement, and in others by fitting the exper [mental disordered layer within approximately 100 of the inthe base results. In devices with a deliberately grown interfacial oxide, terface. current is suppressed to such an extent that recombination in the sinSuccessful modeling of polysilicon emitter transistors gle-crystal emitter and in thebase becomes important.

A

I. INTRODUCTION ONSIDERABLE work has been published in tbe literature over the last few years on the use of polycrystalline silicon to improve the performance of hipolar transistors [11, [2]. These polysilicon emitter trani;istors not only provide a simple means of producing veq' shallow junctions, but also a considerable increase in current gain, particularly when a thin interfacial oxide layer is introduced between the polysilicon and single-crysml silicon [ 3 ] . A variety of theoretical models have been proposed to explain the improved gains of polysilicon emitter transistors, and these are broadlyof two types. The first is a tunneling model [l] that explains the improved gain in terms of tunneling through a thin interfacial oxide layer. The originalmodelwasproposedbydeGraaffand de Groot [l] and later improved by Eltoukhy and Roulston [4]. Recently Van Halen and Pulfrey [ 5 ] have gone so far as to demonstrate that devices withan interfacial lag er can be modeled in exactly the same way as metal-insulator-

C

Manuscript received July 9, 1986; revised January 12, 1987. T lis work was supported under Grant A4321 from the NSERC, Ottawa, Canada. P. Ashburn is on leave with the Department of Electrical Engineering, University of Waterloo, Waterloo, Ontario, Canada. He is with the Department of ElectronicsandInformationEngineering,Universityof Southampton, England. D. J. Roulston and C. R. Selvakumar are with the Department of Electrical Engineering, University of Waterloo, Waterloo, Ontario, C mada. IEEE Log Number 8613905.

across the full range of interfacial oxide thicknesses and processing conditions requires a unified model that incorporatesbothtunnelingandtransportmechanisms.EltoukhyandRoulston[4] have developed such a model that is suitable for numerical implementation, and Yu et al. [9] have developed a similar analytical model, which also includes recombination at the interfacial oxide-single-crystal silicon interface. In an earlier paper [3], Ashburn and Soerowirdjo used simplified models to explainthe characteristics of devices with and without an interfacial oxide. Devices with an interfacial layer were well described by a tunneling model, and those without by a transport model. In this paper, we extend this work by using the unified theory [4] to fully explain the dc characteristics of polysilicon emitter transistors over a much wider rangeof processing conditions. Devices with arsenic- and phosphorous-doped emitters are compared, as well as devices with and without an interfacial oxide. In this way, it is possible to assess under what conditions tunneling or transport limit the base current, and also to assess the importance of other mechanisms such as recombination in the single-crystal emitter and in the base. In addition to the gain, emitter resistance is also considered, and it is shown that a tunneling model canpredict the measuredvaluesof emitter resistance across the full range of processing conditions. 11. THE NUMERICALMODEL An up-dated version of the BIPOLE computer program [ 101 is used for the computer simulations. This program

0018-9383/87/C~600-1346$01.000 1987 IEEE

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ASHBURN et al.: COMPARISON OF RESULTS ON BIPOLARTRANSISTORS

is based on a one-dimensional solution of the semiconductor equations in the vertical (emitter to collector) direction using the variable boundary regional approach; this solution is coupled in the quasi-neutral base region to the horizontal solution (direction ofbase current flow) for majority-carrier drift and diffusion. The program thus includes two-dimensional effects with very good engineering accuracy and has been tested on numerous devices withf, values from 10 MHz to 7 GHz and emitter dimensions from 2 pm X 0 . 8 pm to 100 pm X 3 cm. The program includes bandgap reduction at heavy doping levels [ 111, variation of Shockley-Read-Hall and Auger recombination withdoping [12], and mobility versus doping ~131. The modifications used in the present work, concern the polysilicon and thin oxide layers. Theoriginal multigrain model [4] has been simplified to the case of a single columnar grain structure since this has been reported by several workers to be typical of polysilicon emitter devices [ 141. Thermionic emission has been added as a possible transport mechanismthrough the thin interfacial oxide layer. The solution for aspecified electron current density is used to compute the effective recombination velocity S,, at the monocrystalline surface [15]; this is then used to establish the boundary conditions for minority-carrier transport through the monocrystalline emitter. In the BIPOLE version used in the present work, the following modeling assumptions are made:

1) The thin interfacial oxide is characterized by a uniform layer of knownthickness 6, with known barrier height to holes X h , and electrons xe tunneling through the barrier. 2, The polysilicon layer is assumed doped' 3) Only Auger recombination is included in the polysilicon layer. 4) Interface states are neglected. 5, i' doping dependent' The given in Li3i is used in the polysilicon layer with a user-adjustable multiplier RMv. 111. FABRICATION DETAILSAND EXPERIMENTAL RESULTS The devices were fabricated on (loo), 2.5-pm-thick, n on n+ epitaxial material, with a resistivity of approximately 0.5 0 cm. Wherever possible the transistors were given identical processing, the major exception being the surface treatment prior to polysilicon deposition, where half were given an RCA clean and the rest on an HF etch as described previously [3]. The LPCVD polysilicon was 4000 thick and a dose of 1 X 10l6 cmP2was used for the emitter implant. A drive-in of 30 min at 900°C was used for the arsenic and 10 min at 900°C for the phosphorus. This shorter drive-in was necessary becauseof the larger diffusion coefficient of phosphorus compared with arsenic. Electrical measurements were made on devices with a nominal emitter area of 6 X 6 pm2 and a single base contact. A minimum of ten devices were mea-

-

A

Lo

Io

-~

U H

m H

IO P

Io

-~

0 AS

0 As

- DOPED

RCA

- DOPED H F

m P

-DOPED FICA 0 P -DOPED HF

'""06

07

0.8 09 VBE, volts

i 0

1.1

Fig. 1. Measured base and collector current ( VcE = 5 V ) as a function of V,, for arsenic-doped RCA ( 0 ) and HF ( 0) devices, and for phosphorus-doped RCA ( W ) and HF ( 0) devices. TABLE I COMPARISON OF THE MEASURED AND COMPUTED EMITTER RESISTANCE DOPANT

1,

INTERFACE

1

~~ATIIElTl

POLYSILICON SHEET RESISTANCE nlsq.

EMITTERRESISTANCE R MEASURED COMPUTED 'BE < 0.8v 'BE

1

5.0

RCA

0.1

I

-

1.3v

5.6 0.4

1.1 1.1

I

sured fromeachwaferand the results presented here are typical of the results obtained. Fig. 1 shows the measured collector and base current characteristics of the devices used in this paper. The collector characte-istics of the two arsenic-doped devices are very similar, indicating that the two interface treatments yield comparable emitter-base junction depths and hence similar baseGummelnumbers. Howeve;, for the two phosphorus-doped devices, the collector characteristics lie at higher currents, indicating that the phosphorous has penetrated deeper into the single-crystal silicon than the arsenic, in spite of the shorter drive-in time. This conclusion was confirmed by measurements of the sheet resistance of the base under the emitter. It can also be seen from Fig. 1 that the collector current for the HF-treated device is higher than that for the RCA devices. This can be explained by retardation of the emitter diffusion, due to thepresence of the interfacial oxide, asreported earlier [16]. For the phosphorous-doped RCA device, there was some evidence of recombination in the base. For example, decreasing the collector-base voltage from 5 to 1 V leads to an increase in base current by a factor of nearly 2. The values of emitter resistance. obtained on these devices have been reported previously 1171 and are summarized in Table I for convenience.

1348

TRANSACTIONS IEEE

ON ELECTRON DEVICES, VOL. ED-34, NO. 6, JUNE 1987

rn,

Here A, is the modified Richardson constant, xe the effective barrier height for electrons, the effective mass in the insulator, Vo the voltage drop across the insulator, 6 the interfacial layer thickness, and V, ( V,) the band-bending adjacent to the left (right) of the interfacial layer 141. In heavily doped polysilicon, the band-bending at the interface due to interface states ( V , and V,) is negligible and can be ignored in the above equation. In this case, (1) can be simplified to

0.8

09

IO

1.1

1.2

1.4

1.3

1.5

1.6

VBE, volts

Fig. 2. The computed voltage drop across the interfacial oxide V,,, divided by the collector current IC,plotted as a function of base-emittcx voltage for a variety of interfacial oxide thicknesses. The dashed line :;bows the conditions under which the expression q C e V o / 2 = 0.2 is satisffied.

IV. DISCUSSION A. Emitter Resistance Fig. 2 shows a graph of the computed emitter resistance, obtained by dividing the computed volta!:le drop across the interfacial oxide by the electron tunneling current as a function of base-emitter voltage. An dectron effective barrier height of 0.4 eV (obtained by fitti mg-see below) and an emitter doping of 8 X 1019cmW3wcre used in the calculations, and results are shown for a variety of interfacial layer thicknesses. It can be seen that below a voltage of about 0.8 V, the emitter resistance is constant, indicating that the interfacial oxide is giving rise to a purely ohmic voltage drop. Above a voltage of 0. li V, the emitter resistance decreases with base-emitter wltage, and this decrease is more pronounced for the thicker oxides. In this region of the characteristics, the emitter resistance is far from ohmic, particularly for the thkker inA, terfacial oxides. At this point it is useful to pause and consider the explanation for the predictions in Fig. 2. The electron current in a polysilicon emitter transistor and as implcmented in the BIPOLE program can be written as [4]

. [exp

where

(-9% !&%) kT +

2

For interfacial oxide thicknesses of practical interest, (