CML and ECL: optimized design and comparison

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CML and ECL: Optimized Design and Comparison Massimo Alioto and Gaetano Palumbo, Senior Member, IEEE

Abstract— In this paper a pencil-and-paper optimized design for current mode logic (CML) and emitter coupled logic (ECL) gates is proposed. The approaches are based on simple models which show errors lower than 20% as compared with Spice simulations. The optimization is performed in terms of bias currents, which give the minimum propagation delay, and it is demonstrated that at the cost of a 10% increase in propagation delay we can reduce the power dissipation by 40%. Strategies to optimize the transistor area of the CML gates are also discussed. A comparison between the optimized CML and ECL is made. It shows the advantage of the CML gate with respect to the ECL in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. The simple models and the design strategies are validated by using both a traditional and a high-speed bipolar process, which have transition frequencies equal to 6 and 20 GHz, respectively. Index Terms— Bipolar transistor circuits, bipolar transistor logic devices, current mode logic, digital circuits, digital integrated circuits, emitter coupled logic, high-speed integrated circuits, switching circuits.

I. INTRODUCTION

D

UE TO their high-speed switching properties, current mode logic (CML) and emitter coupled logic (ECL) are employed in many high-speed digital systems and subsystems [1]–[17]. In the design of these bipolar digital circuits, minimization of the propagation delay is a fundamental step. This target must be achieved with the lowest power dissipation. The strategies proposed up to now for the design of CML and ECL gates are not simple and are impractical in a pencil-and-paper approach [18]–[22]. Indeed, the different approaches proposed in the literature to evaluate the delay expression of CML and ECL gates, such as sensitivity analysis [18]–[20], linearization of the device models [22]–[24], and others [25], [26], have not led to models which are simple for designers to use. Efficient models for a pencil-and-paper design must provide a good level of accuracy and be composed of only a few parameters. In this paper, optimized design strategies for CML and ECL gates are proposed. The strategies are based on simple propagation delay models of CML and ECL which, in the range of interest, have errors lower than 20%, and are, hence, sufficiently accurate for a pencil-and-paper design. The models are validated by using both a traditional and a high-speed bipolar process, which have transition frequencies equal to 6 and 20 GHz, respectively. Manuscript received April 1, 1998; revised March 17, 1999. This paper was recommended by Associate Editor K. Roy. The authors are with Dipartimento Elettrico Elettronico e Sistemistico, Universit´a di Cantania, I-95125 Catania, Italy. Publisher Item Identifier S 1057-7122(99)09266-1.

Fig. 1. CML gate.

To perform the design, the bias current values which minimize the propagation delay of the gates are found. Moreover, we demonstrate that at the cost of a 10% increase in propagation delay, we can reduce the power dissipation by 40%. Finally, a comparison between optimized CML and ECL is made. It shows the advantage of the CML gate with respect to the ECL in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. Indeed, the optimum bias currents for ECL is independent of the load, while that of the CML gate increases with the load. II. CML

AND

ECL PROPAGATION DELAY

A. CML Model A CML gate is shown in Fig. 1. In order to achieve highspeed performance its transistors work in a linear region and can be represented with a linearized model. Moreover, since the circuit is symmetrical, and differential operation is assumed, we can limit our analysis to the half-circuit model in and input resistance are Fig. 2. The transconductance and , those of the small signal model and are resistive respectively, and the resistances is composed by a parasitics. The base-emitter capacitance and a junction capacitance, diffusion capacitance (1) , is split into an intrinsic The base-collector capacitance, and an extrinsic one to take its distributed nature part , which into account by using the technological parameter, ranges between zero and one

1057–7122/99$10.00  1999 IEEE

(2a) (2b)

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Fig. 2. CML half-circuit model.

Finally, the collector-substrate capacitance is only a junction capacitance. However, since voltages move rapidly over a wide range, unlike the traditional small signal model, we must properly evaluate the diffusion and junction capacitances, as shown in Appendix A [18], [27]. Assuming a dominant pole behavior with a time constant , the propagation delay, is equal to . Thus, by inspection of the circuit in Fig. 2, and neglecting the term , we get

(3) Fig. 3. ECL gate.

The propagation delay is the sum of four main terms which have a simple circuit meaning. The first term is the contribution made by the base-emitter capacitance, the second is made by the Miller effect on the intrinsic base-collector capacitance,1 the third is a contribution which arises at the inner collector node (i.e., before the parasitic resistance ), and the last one is due to the load capacitance at the output node. B. ECL Model An ECL gate, as shown in Fig. 3, is a symmetrical gate made up of a CML followed by common-collector (CC) stage. Again, we assume all the transistors to be working in a linear region. Therefore, we can consider only half of the circuit and assume the ECL propagation delay to be composed by two separate contributions; the CML propagation and the common-collector propagation delay delay . More specifically, we represent the CML with an equivalent Thevenin model and, hence, evaluate its propagain relationship (3)]. tion delay without a load i.e., Thus, the input voltage of the CC is modeled with a voltage 1 The term g =(1 + g r ) is the equivalent transconductance of the m m e transistor having a resistance re at the emitter node. This resistance creates a local feedback which reduces the transconductance value.

Fig. 4. CC half-circuit model driven by CML stage.

source, with the associated propagation delay hav. Thus, we can evaluate the CC ing an output resistance propagation delay from the input of the Thevenin generator to the load, taking into account output resistance of the CML stage. Analyzing the linear model of the CC stage depicted in Fig. 4, where in order to simplify the model the base-collector

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parasitic is not split2 and a zero at a frequency much higher than that of the poles has been neglected, we get (4), shown at the bottom of the page.3 Usually, (4) has two complex and conjugate poles which, in the time domain, gives the following normalized step response:

TABLE I 6-GHz TECHNOLOGY

(5) where the pole frequency

and the damping factor

TABLE II 20-GHz TECHNOLOGY

are (6a)

In conclusion, the propagation delay of the ECL gate can be written as (6b) It is worth noting that, unlike the CML case, the minimum and maximum direct voltage across the base-collector junction are and , where is the swing now ). of a branch, (i.e., half the swing of the gate equal to Moreover, since the voltage across the base-emitter junction of the CC can be assumed to be constant, we can use its small signal value. The CC propagation delay normalized to the inverse of the [i.e., ] depends only pole frequency on the damping factor and for a typical range of , which is from 0.1 to 0.8, its behavior is quite linear and ranges from between and 1 to 1.6 [interpolation of gives ]. Hence, using the worst case value we get (7) Relationship (7) is similar to that given in [28], but the squareroot coefficient has a different value. Moreover, it shows the dependence of the CC propagation delay on the bias current ). ( 2 The assumption is justified since, in this case, the base-collector parasitic is not magnified by the Miller effect and makes a very small contribution. 3 In the coefficient of the term s2 the product C (C bc be + CL ) has been neglected with respect to Cbe CL :

(8)

where the indexes one and two refer to the CML and the CC, respectively. C. Model Validation In order to evaluate the accuracy of the propagation delay model of the CML and ECL given by (3) and (8), respectively, a comparison with Spice simulations was made. Moreover, to generalize the comparison, two different technologies were taken into consideration. The former is a BiCMOS technology whose n-p-n bipolar transistor has a transition frequency equal to 6 GHz, the second is a high-speed bipolar technology whose n-p-n transistor has a transition frequency equal to 20 GHz. The circuits have a 5-V power supply and a 250-mV logic swing for one branch which, for the CML gate, determines the junction capacitances given in Tables I and II for the 6and 20-GHz technology, respectively. Tables I and II also include the minimum and maximum direct voltages across the junction, the built-in potential, the grading coefficient,

(4)

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Fig. 5. Propagation delay of CML for 6-GHz technology.

Fig. 6. Propagation delay of CML for 20-GHz technology.

TABLE III USEFUL TECHNOLOGICAL PARAMETERS

the zero-bias capacitance, and the resulting . Other useful technological parameters are included in Table III, where is the high injection current level. The analytical and simulated propagation delay of CML , with a load capacitance equal versus the bias current to 0 and 100 fF and 1 pF, are plotted in Figs. 5 and 6 for the 6- and 20-GHz technology, respectively. The error found for the two technologies outside the high-level injection region is plotted in Figs. 7 and 8. Except for the CML with 20-GHz technology without load capacitance, which represents an unrealistic situation, the worst case error of the CML model is lower than 20%. equal to 100 fF and 1 pF, Setting the load capacitance for the ECL gate, the errors found between (8) and Spice are plotted in Figs. 9 and 10. The load capacitance was set to 0.1 and 1 pF, and the bias current of the CC stage was set to

Fig. 7. Errors of the simple CML model for 6-GHz technology.

0.4 mA; 0.8 mA; 1 mA and 0.4 mA; 1 mA; 1.8 mA for the 6and 20-GHz technology, respectively. The worst case errors found are much lower than 20% for both technologies. III. CML OPTIMIZED DESIGN A. Design with Unitary Area As shown in the above section, the model is sufficiently accurate to be used during pencil-and-paper design. Neglecting

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(a) Fig. 8. Errors of the simple CML model for 20-GHz technology.

(b) Fig. 10. (a) Errors for simple ECL model with 20-GHz technology and = 100 fF. (b) Errors for simple ECL model with 20-GHz technology and CL = 1 pF.

CL

(a)

(9d) and setting the result to zero, the Deriving (9a) for is achieved by setting the minimum propagation delay bias current to (b)

(10)

Fig. 9. (a) Errors for simple ECL model with 6-GHz technology and = 100 fF. (b) Errors for simple ECL model with 6-GHz technology and CL = 1 pF.

CL

and it is equal to with respect to one, relation (3) can be written versus the bias current (9a) where

, and

are

(9b) (9c)

(11) It is worth noting that the power-delay product always increases when the bias current increases, which means that the gate efficiency increases as the bias current is reduced. Reduced power dissipation is one of the main features of modern digital circuits. Hence, a design strategy to achieve both high speed and reduced power dissipation is a target to pursue. To clearly represent the tradeoff between power and between the propagation delay, we introduce the ratio , (i.e., ). delay and its optimum value Representing it versus parameter , which is the bias current

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(14b) Optimizing to the parameter

, we get

(15) and

(16) Fig. 11.

Normalized propagation delay versus normalized bias current.

normalized to get4

, from (9) to (11) we

(12) is independent of the circuit and The expression of process parameters. Moreover, inspection of its plot, as shown in Fig. 11, shows that a reduction in the bias current around lower than one) only determines its optimum value (i.e., a small increase in the resulting propagation delay. A bias current equal to half the optimum value increases the propagation delay by only 25%, but a lower bias current value leads to an unacceptable increase in the propagation delay (a 40% reduction in the bias current with respect to the optimum value gives a 50% increase in the propagation delay). In our opinion, a good tradeoff between power and speed is (i.e., a bias current equal to 60% achieved by setting of the optimum value). This choice determines a propagation delay which is only 10% worse than the optimum value, while it reduces the power dissipation by 40% with respect to that needed in optimum design. B. Design with Nonunitary Area

and are equal to and , where respectively. Since the term in the square root of (16) is lower than one, we can reduce the propagation delay of the CML gate by increasing its area, but this needs a further power is much dissipation. More specifically, when the ratio higher than one, the reduction in the propagation delay and the (i.e., increase in the bias current are both proportional to the power-delay product is that of the unitary transistor). In this case, the efficiency of the CML is equal to that achieved by optimizing with a unitary transistor, but to reduce delay we spend a proportional amount of power. On the other hand, with a small capacitive load, the reduction in delay is low compared to the increase in bias current, which is proportional to . Hence, an inconvenient amount of power dissipation is needed. Unless there are very heavy speed constraints, since the other fundamental target is usually to minimize power dissipation, the above approach is seldom useful. Thus, in the following paragraphs further considerations on delay reduction, using the current which optimizes the unitary area, are made. To this aim, consider (13) for the fixed bias current value and optimize it for parameter (i.e., derive it for and, setting the result to zero, solve for an integer ). We get (17)

unitary transistors, Considering a transistor made up of , and and capacitances and assuming the resistances , and to be those of the unitary transistor, (9a) must be rewritten as

The number of transistors which reduce the propagation delay is equal to the ratio of the optimum current with a unitary area and the optimum current with a unitary area evaluated without a load capacitance. By substituting (10) and (17) in (13) we get

(13) (18) where

and

are given by (9b) and (9d) and

pab.

and

are (14a)

p = ab,

the c is lower than Moreover, even with c for common values of IN greater than 0.5, the error on the approximated expression of (9) is lower than 7%. 4 Usually,

Comparing (18) with the propagation delay with a unitary area , expressed by (11), we found that optimization of the allows us to reduce area by setting the bias current to the propagation delay at the cost of an increased area.

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The increase in transistor area can also be useful when , gives a the optimum current for the unitary case, nonnegligible high injection level which reduces transistor performance. However, it is worth noting that the increase in area from the unitary value, according to the results given in Appendix B, leads to a proportional increase in the input capacitance of the CML gate. Thus, if the gate under design is the main load of a previous gate, it may not be convenient to design a transistor with a nonunitary area. C. Design Example In order to illustrate the proposed procedure in detail, CML gates with both the 6-GHz technology and the 20-GHz technology, assuming the fan-out to be equal to one and ten, are designed. The gates are powered with 5 V and have mV, thus, Tables I–III can be used. According to Appendix B, for the 6-GHz technology, the two load conditions are equivalent to a 120-fF and 1.2-pF load capacitance. The optimum bias currents are 0.7 and 1.8 mA, which leads to a propagation delay of 129 and 277 ps (the values are very close to those given by Spice simulations which are 126 and 276). For a fan out of 10 the current is slightly higher than the high-injection level, but there is no appreciable degradation in the propagation delay. However, since the optimum current is 0.4 mA, according to (17) we can evaluated without further reduce the propagation delay to 166 ps, setting the number of unitary transistors equal to four. In this case, the simulated value is 15% higher than that predicted analytically. With the 20-GHz technology, the two fan-out conditions are equivalent to a 100-fF and 1-pF load capacitance. The optimum bias currents are 3.4 and 9.4 mA, which leads to a nominal propagation delay of 19 and 42 ps. While for the former case the analytical results are very close to the Spice simulation, which gives 21 ps, with the bias current of 9 mA, the transistors work strongly in the high-injection region and the analytical propagation delay obtained is not realistic. According to (17), we set the number of unitary transistors to three. Thus, we reduce the nominal propagation delay to 30 ps, which differs from the simulated value by 10%, and avoid the strong condition of high injection. Reduction in the power dissipation can be achieved by reducing the bias current by 40%, which only leads to a small increase in the propagation delay. IV. ECL OPTIMIZED DESIGN Both the ECL gate and its propagation delay are composed by two main parts, thus, we can split the optimized design into of the CML two steps. First, we must find the bias current . Following stage to optimize its propagation delay, the same strategy as in the previous section, and setting the to zero, from (10) we get load capacitance

delay. During the falling signal transition, if the emitter voltage cannot follow the base voltage at the same speed, the CC stage cuts off, resulting in a much larger average delay with respect to the value resulting from relationship (7), which holds when the CC stage works in the linear region. As a consequence, we must guarantee that the CC stage works in an almost linear region. A simple design strategy to satisfy this condition was proposed in [28]. It is based on the consideration that the medium current value which discharges the load capacitance is . Thus, they set the bias current equal to it [i.e., ]. A bias current greater than this critical value does not substantially reduce the delay. However, this choice has two drawbacks. on the value of The first is the dependence of (i.e., the dependence of on itself). The second is the linear on the load capacitance , which can dependence of determine too high a power dissipation. To overcome these drawbacks we propose the approach outlined below. The propagation delay of the common collector in (7) can be written as

(20) is the asymptotic value of reached where [i.e., ]. for versus the ratio Hence, we can represent the bias current as (21) , the By simulation, we found that, for a value of values maintain the CC stage in an almost linear resulting region. Then during the falling signal transition . As a consequence, we can use (21) to choose the value. In particular, our rule of thumb to achieve a low CC propagation delay (i.e., near to the asymptotic value) with a low power dissipation, suggests setting . It is worth noting that for usual load capacitance values, (21) gives a lower bias current than that resulting from [28].5 Following this approach, the power dissipation of the optimized ECL is seen to be independent of the load capacitance. It is, in fact, composed of the CML and CC stage contributions, which are constant. 5 Although the approach in [28] leads to lower bias current for lower load capacitance, it needs lower bias current than the proposed one for load capacitance

(19)

CL < Then we must choose the minimum bias current of the CC stage which allows us to have an acceptable CC propagation

5

n0

( 2

1)2

VT

VS

which is an unrealistic load capacitance.

2 C2 2 C 2

2 je  Cje 2 CD 2 D

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(a)

(b) Fig. 12. (a) Propagation delay versus (20-GHz technology).

CL

for optimized design (6-GHz technology). (b) Propagation delay versus

In order to reduce power dissipation, we can again use a bias 40% lower than the value resulting from (19). current

for optimized design

are very close to those given by Spice simulations, which are 28 and 86 ps, respectively. V. COMPARISON BETWEEN CML

C. Design Examples Consider the 20-GHz technology and design the ECL gate for a fan out of one and ten. The optimum bias currents are mA independent of the load and their values are mA. The propagation delay of the differential and stage is also independent of the load, and its value is 12 ps. Thus, the resulting propagation delays are 30 and 72 ps for a load capacitance of 0.1 and 1 pF, respectively. These values

CL

AND

ECL

To compare the speed performance of CML and ECL we write the CML propagation delay as (22) where (23)

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(a)

(b) Fig. 13.

(a) Total bias current versus CL for optimized design (6-GHz technology). (b) Total bias current versus CL for optimized design (20-GHz technology).

and the ECL propagation delay as (24) , we find that Solving the inequality , which is generally true for highwhen is always lower than . speed technologies, On the other hand, the inequality holds for

assumption, this property also holds for a high capacitive load. To illustrate this further, in Fig. 12(a) and (b) the propagation delay of optimized CML and ECL gate are plotted versus the load capacitance for the 6- and 20-GHz technologies. The drawback to the CML gate could be the higher power consumption. Indeed, the optimized CML add ECL require the bias current to be (26)

(25) where the value given by the ratio is usually greater than one. In conclusion, with modern technologies CML gates always have a better speed than ECL gates. Contrary to the traditional

(27)

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(a)

(b) Fig. 14. (a) Power-delay product versus (20-GHz technology).

CL

for optimized design (6-GHz technology). (b) Power-delay product versus

CL

for optimized design

the 20 GHz technology the CML needs more power for a load capacitance higher than 0.1 pF. Finally, to show the tradeoff between power and speed of the CML and ECL gate, the power delay products are depicted in Fig. 14(a) and (b). It is apparent that the power delay product of the CML gate is always better than that of the ECL gate. The same consideration can be made for CML and ECL gates designed with a bias current 40% lower than the optimum value.

and (26) is lower than (27) for a load capacitance of

(28) More specifically, according to the results plotted in Fig. 13(a) and (b), with the 6-GHz technology the CML needs less power than the ECL up to a load capacitance of 0.6 pF, while for

VI. CONCLUSION In this paper strategies to design CML and ECL gates are proposed. The approaches are based on simple models, whose

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Fig. 15.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 11, NOVEMBER 1999

Equivalent circuit for evaluation of a gate input capacitance.

accuracy is sufficient to perform a pencil-and-paper design. Indeed, the models show errors lower than 20% with respect to Spice simulations. The design strategies allow us to set the bias current which gives the best propagation delay. Moreover, it is demonstrated that, by reducing the power dissipation by 40%, we lose only 10% of the speed. The CML gate is also optimized in terms of area but, since the optimum bias current proportionally increases with the area, this strategy needs too high a power dissipation. Hence, it is advisable to optimize the area setting the current to the optimum value for a unitary transistor. This choice can be useful both to reduce the propagation delay of the gate and to avoid a high injection region. However, the increase in area determines a proportional increase in the input capacitance and, if the gate under design is the load of a previous gate, the area must be left unitary to avoid a high injection current. The design of the ECL is achieved by optimizing the two main blocks, which are the inner CML and the CC. More specifically, the CML is designed assuming a load capacitance equal to zero and the CC is designed by setting the propagation delay to a percentage of its asymptotic value. The simple models and the design approaches were validated with two different technologies, and Spice simulation agrees well with the analytical results. Finally, a comparison between optimized CML and ECL was made. The comparison demonstrated that the CML can achieve the lowest propagation delay, but this is sometimes at the cost of power dissipation. APPENDIX A EVALUATION OF THE PARASITIC CAPACITANCES The diffusion capacitance,

where is the built-in potential across the junction, is the and are the grading coefficient of the junction, and minimum and maximum direct voltage across the junction, respectively. APPENDIX B OF THE INPUT CAPACITANCE OF CML AND ECL

EVALUATION

By inspection of the circuit in Fig. 2, neglecting the parasitic resistance , and applying the Miller theorem on the intrinsic and extrinsic base-collector capacitance, the input impedance can be represented with the linear circuit in Fig. 15. The worst case arises when the capacitance in parallel with the resistance is short circuited. Thus, the equivalent input capacitance of a CML and ECL gate can be assumed to be (B1) Relationship (B1) gives a value of 138 and 109 fF for the 6and 20-GHz technologies, respectively. Since by simulation we found that a capacitive load equivalent to a CML or ECL load is 120 and 100 fF for the 6- and 20-GHz technologies, respectively, an error lower than 15% is found. ACKNOWLEDGMENT The authors would like to thank ST Microelectronics and, in particular, Ing. G. Ferla and Ing. S. Sueri for having allowed us to use the Spice model of the HSB2 technology. They are grateful to the reviewers for their useful comments. REFERENCES

, is given by [18] (A1)

is the transistor transit time. The junction cawhere are modified from their value in a zero-bias pacitances , via coefficients given by [27] condition (A2)

[1] G. Wilson, “Advances in bipolar VLSI,” Proc. IEEE, vol. 78, pp. 1707–1719, Nov. 1990. [2] M. Kurisu et al., “A Si bipolar 21-GHz/320-mW static frequency divider,” IEEE J. Solid-State Circuits, vol. 26, pp. 1626–1630, Nov. 1991. [3] C. Stout and J. Doernberg, “10-Gb/s silicon bipolar 8 : 1 multiplexer and 1 : 8 demultiplexer,” IEEE J. Solid-State Circuits, vol. 28, pp. 339–343, Mar. 1993. [4] K. Ishii et al., “Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops,” IEEE J. Solid-State Circuits, vol. 30, pp. 19–24, Jan. 1995.

ALIOTO AND PALUMBO: CML AND ECL: OPTIMIZED DESIGN COMPARISON

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[5] Z. H. Lao et al., “A 12 Gb/s Si bipolar 4 : 1-multiplexer IC for SDH systems,” IEEE J. Solid-State Circuits, vol. 30, pp. 129–132, Feb. 1995. [6] L. I. Andersson et al., “Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links,” IEEE J. Solid-State Circuits, vol. 30, pp. 210–217, Mar. 1995. [7] K. Kawai et al., “High speed regenerator-section terminating LSI operating up to 2.5 Gbit/s using 0.5 m Si bipolar standard-cell technology,” Electron. Lett., vol. 31, pp. 791–792, May 1995. [8] N. Ishihara et al., “3.5-Gb/s 4-Ch Si bipolar LSI’s for optical interconnections,” IEEE J. Solid-State Circuits, vol. 30, pp. 1493–1500, Dec. 1995. [9] Z. Lao et al., “Si bipolar 14 Gb/s 1 : 4-demultiplexer IC for system applications,” IEEE J. Solid-State Circuits, vol. 31, pp. 54–59, Jan. 1996. [10] Z. Lao and U. Langmann, “Design of a low-power 10 Gb/s Si bipolar 1 : 16-demultiplexer IC,” IEEE J. Solid-State Circuits, vol. 31, pp. 128–131, Jan. 1996. [11] A. Felder et al., “46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology,” IEEE J. Solid-State Circuits, vol. 31, pp. 481–486, Apr. 1996. [12] H. Rein, “Design consideration for very-high-speed Si-bipolar IC’s operating up to 50 Gb/s,” IEEE J. Solid-State Circuits, vol. 31, pp. 1076–1090, Aug. 1996. [13] F. Sato et al., “A 2.4 Gb/s receiver and a 1 : 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor,” IEEE J. Solid-State Circuits, vol. 31, pp. 1451–1456, Oct. 1996. [14] J. Hauenschild et al., “A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1 : 4-demultiplexer with external VCO,” IEEE J. Solid-State Circuits, vol. 31, pp. 2056–2059, Dec. 1996. [15] K. Kishine, Y. Kobayashi, and H. Ichino, “A high-speed, low-power bipolar digital circuit for Gb/s LSI’s: Current mirror control logic,” IEEE J. Solid-State Circuits, vol. 32, pp. 215–221, Feb. 1997. [16] K. Lowe, “A GaAs HBT 16 16 10-Gb/s/channel crosspoint switch,” IEEE J. Solid-State Circuits, vol. 32, pp. 1263–1268, Aug. 1997. [17] M. Mokhtari et al., “InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V,” IEEE J. Solid-State Circuits, vol. 32, pp. 1371–1382, Sept. 1997. [18] D. D. Tang and P. M. Solomon, “Bipolar transistor design for optimized power-delay logic circuits,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 679–684, Aug. 1979. [19] E.-Chor, A. Brunnschweiler, and P. Ashburn, “A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes,” IEEE J. Solid-State Circuits, vol. 23, pp. 251–259, Feb. 1988. [20] W. Fang, “Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits,” IEEE J. Solid-State Circuits, vol. 25, pp. 572–583, Apr. 1990. [21] W. Fang, A. Brunnschweiler, and P. Ashburn, “An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers,” IEEE J. Solid-State Circuits, vol. 25, pp. 920–931, Aug. 1990. [22] K. M. Sharaf and M. I. Elmasry, “Analysis and optimization of seriesgates CML and ECL high-speed bipolar circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 202–211, Feb. 1996. [23] , “An accurate analytical propagation delay model for high-speed CML bipolar circuits,” IEEE J. Solid-State Circuits, vol. 29, pp. 31–45, Jan. 1994.

[24] Y. Harada, “Delay components of a current mode logic circuit and their current dependency,” IEEE J. Solid-State Circuits, vol. 30, pp. 54–60, Jan. 1995. [25] A. T. Yang and Y. Chang, “Physical timing modeling for bipolar VLSI,” IEEE J. Solid-State Circuits, vol. 27, pp. 1245–1254, Sept. 1992. [26] M. Ghannam, R. Mertens, and R. Van Overstraeten, “An analytical for the determination of the transient response of CML and ECL gates,” IEEE Trans. Electron Devices, vol. 37, pp. 191–201, Jan. 1990. [27] J. Rabaey, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, 1996. [28] G. K. Konstadinidis and H. H. Berger, “Optimization of buffer stages in bipolar VLSI systems,” IEEE J. Solid-State Circuits, vol. 27, pp. 1002–1013, July 1992.

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Massimo Alioto was born in Brescia, Italy, in 1972. He received the Laurea degree in electronics engineering from the University of Catania in 1997 where he is now working toward the Ph.D. degree. His primary research interests are in the areas of bipolar and CMOS high-performance digital circuits in terms of high speed or low power dissipation.

Gaetano Palumbo (M’91–SM’98) was born in Catania, Italy, in 1964. He received the Laurea degree in electrical engineering and the Ph.D. degree from the University of Catania in 1988 and 1993, respectively. In 1993, he conducted a course on electronic devices for the diploma degree in electronics engineering and now teaches a course on electronics for digital systems and a first course in electronics. In 1994, he joined the Department of Electrical Electronics and System (DEES) at the University of Catania as a Researcher and is now a Professor in the same department. His primary research interests were in the areas of analog circuits, with particular emphasis on feedback circuits, compensation techniques, currentmode approach, and low-voltage circuits. Recently, his research has involved digital circuits, with emphasis on ECL and CML and implementations of protocol for home and building automation. He is currently developing research projects in these areas in collaboration with ST Microelectronics of Catania. He is coauthor of the book CMOS Current-Mode Amplifier (Kluwer, 1999) and author or coauthor of more than 100 scientific papers in referred international journals and conferences. Dr. Palumbo received a grant from AEI of Catania in 1989. He is currently serving as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I