Bulk defect induced low-frequency noise in n/sup +/-p silicon diodes

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Bulk Defect Induced Low-Frequency Noise in n -p Silicon Diodes Fan-Chi Hou, Gijs Bosman, Senior Member, IEEE, Eddy Simoen, Jan Vanhellemont, and Cor Claeys

Abstract— The low-frequency 1=f -like noise of gated n+ -p silicon diodes has been measured and analyzed in terms of trapping and detrapping of holes in defect centers located in the bulk section of the space charge region at 0.43 eV below the conduction band. Both the trap characteristics and their precise physical location are resolved from the noise measurements showing that the noise producing defect region moves closer to the metallurgical junction when forward bias is increased. The noise measurements independently confirm that thermal substrate pretreatments lower the defect density in the diodes fabricated in Czochralski (CZ) grown substrates. The defect centers are assumed to be associated with precipitated oxygen/dislocation complexes. Index Terms—Charge carrier processes, diodes, semiconductor device noise, trapping noise.

I. INTRODUCTION

I

N AN earlier paper [1], the low-frequency noise data collected on near ideal n -p silicon junction diodes fabricated in four differently grown -type silicon substrates was reported as a function of substrate growth technique, starting substrate pretreatment, and bias current. The lowbehavior with close frequency noise spectra show a 1/ to one but slightly bias dependent. The latter observation eliminates Hooge’s mobility or diffusivity fluctuation model [2] for explaining the data, leaving defect induced noise as the only viable option. Surface and bulk models have been proposed in the literature to account for 1/ -like noise via the McWhorter model of distributed time constants [3], [4], and have shown to apply in a variety of situations. However, a problem that remains to be solved, and which is the topic of this paper, is how to effectively use noise data for identifying the physical location, characteristics, and carrier interaction mechanism of the responsible defect centers in such devices as diodes, where carrier concentrations and energy levels vary strongly with position and bias. For homogeneous resistors, this information can be obtained with great precision from a detailed noise analyses [5]. Noise spectroscopy for identifying defect centers has the advantage that only the properties of centers, which actually affect device performance, are probed in as-made devices; no special test structures are needed. Manuscript received April 29, 1998; revised July 14, 1998. The review of this paper was arranged by Editor James M. Hollenhorst. F.-C. Hou and G. Bosman are with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611 USA. E. Simoen and C. Claeys are with IMEC, B-3001, Leuven, Belgium. J. Vanhellemont was with IMEC, B-3001, Leuven, Belgium. He is now with Wacker Siltronic AG, D-84479 Burghausen, Germany. Publisher Item Identifier S 0018-9383(98)09028-5.

Fig. 1. Gate capacitance measured between the gate and substrate terminals as a function of VGS for various values of VES . Insert: schematic cross section of a gated diode.

For the present study large area, gated n -p diodes were fabricated in Czochralski grown silicon substrates containing a high concentration of interstitial oxygen (O ). One substrate was processed as is, while the other underwent high temperature pretreatment steps to modify bulk defect densities and distributions. A gate terminal was incorporated in the device design so that the surface charge state and thus any surface noise could be modulated by an applied gate bias. A detailed device description is presented below. II. DEVICE FABRICATION AND DEFECT CHARACTERIZATION The diodes to be studied were fabricated in two p-type Czochralski silicon wafers with a background concentration of 10 boron atoms/cm . Inherent to the manufacturing process of CZ crystals is the unintentional incorporation of oxygen atoms which occupy interstitial lattice sites and are present in supersaturation at most device processing temperatures. During thermal treatments the excess of interstitial oxygen precipitates resulting in the formation of electrically active lattice defects acting as trapping or recombination centers. Fourier transform infrared (FTIR) spectroscopy confirmed that the interstitial oxygen content (O ) of both CZ wafers was 10 cm before any thermal pretreatments [6]. One 9 wafer, CZ no, was processed as is, while the other, CZ IG, was subjected to a full internal gettering (IG) thermal treatment

0018–9383/98$10.00  1998 IEEE

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Fig. 2. AC measurement setup.

before device fabrication consisting of the following three steps. In the first step, called denuded zone formation, the CZ wafer was exposed to a nitrogen atmosphere with 5% oxygen at 1100 C for 6 h. The wafer was then subjected to an ambient of nitrogen for 8 h at 750 C in a process leading to nucleation. The final treatment, called precipitate growth, was the field oxidation step of the CMOS compatible diode process during which the wafer was heated at 975 C for 10 h. Transmission electron microscopy (TEM) measurements [6] show that approximately a 10- m-wide layer with reduced oxide precipitate density beneath the surface of the CZ IG wafer results from the IG thermal treatment. Both CZ no and CZ IG wafers were implanted with 80 keV 10 and As atoms and 130 keV P atoms to a dose of 4 10 ions/cm , respectively, to create a junction area of 3 900 m and an approximately 0.5- m-thick n 900 m emitter layer. The purpose of using large diodes in this study is to minimize the effect of the perimeter on noise data. The doping concentration of the n layer was found to be 10 donor atoms/cm . The gate oxide, grown in dry O at 975 C, has a thickness of 17 nm and is directly below the 900 m 920 m, 450-nm-thick polysilicon gate terminal. Since the ohmic contact of the substrate terminal is on the backside of the wafer, the width of the p-region of the diode equals the thickness of wafer, which is approximately 600 m. The diodes on each wafer are isolated from one another by local oxidation of silicon (LOCOS). A schematic cross section of the gated n -p diode is shown in the insert of Fig. 1. In the following the n and p contacts will be referred to as emitter and substrate contacts, respectively. After diode fabrication deep-level transient spectroscopy (DLTS) revealed two energy and at 0.17 and 0.43 eV below the conduction levels , respectively. The capture cross section of band edge was estimated to be 10 cm [6].

and in series, where is defined as the capacitance of the surface space charge region (SCR) at the silicon-oxide interface. The width and onset of this SCR is a function and . Hence, the gate bias voltage range of both for surface accumulation, depletion, and inversion modes for can be determined from a plot of the gate any specific versus gate bias voltage , as shown in capacitance V Fig. 1. Using the gate capacitance measured at as an example, surface accumulation, depletion, and inversion , , and modes occurs for V, respectively. B. AC and DC Measurements The schematic diagram of the ac measurement setup is and , generated shown in Fig. 2. The dc voltages by lead-acid batteries, bias the diode under test. The ac and noise voltage at the emitter terminal of the diode is amplified by a Brookdeal 5004 Ultra Low Noise Preamplifier with a gain V/V and sampled by an HP 3582A Fast Fourier of Spectrum Analyzer. To measure the dynamic resistance of the of constant frequency and diode, a small ac voltage amplitude is applied to node (1) of the circuit in Fig. 2. If the , reading at the output of the preamplifier is denoted as at frequency is equal to then (1) is the input resistance of the preamplifier. The where is measured directly on the spectrum input ac signal analyzer as (2) The dynamic resistance of the diode condition equals then

at the given bias

III. MEASUREMENTS AND PARAMETER EXTRACTION A. Capacitance Measurements To determine the charge state of the silicon surface layer beneath the gate oxide, the gate capacitance was measured with an HP 4275A multifrequency LCR meter as a function is of gate-to-substrate voltage. The gate capacitance , where is the change in charge in defined as . When the diode is operating in the surface response to to equal accumulation or inversion mode one expects . In the depletion mode, equals the capacitance of

(3) calculated from measured and The value of under different bias conditions will be used in the delineation of diffusion and recombination current components and to determine the experimental value of the ideality factor . was measured with a HP 4145B The dc bias current and . The Parameter Analyzer as a function of can be separated into a diffusion current current

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TABLE I DC PARAMETERS OF MEASURED GATED DIODES

and a recombination current approximated by

.

and

can be

(4) and (5) is Boltzmann’s constant, and is the device where and represent the diffusion temperature in Kelvin. and recombination saturation currents, respectively. Under is approximately sufficiently high forward bias condition, due to the strong bias voltage dependence of equal to this component. Taking the natural logarithm of (4) results in (6) can be determined from the slope of The bulk resistance versus plot. It was found the is independent of the applied gate bias that the value of , indicating that does not effect the carrier voltage concentration in the bulk region of the substrate. The values for the measured diodes are shown in Table I. of is defined as If the variable , the bias current can be rewritten as (7) Taking the derivative, (7) becomes (8) is the thermal voltage equal to and is where the dynamic resistance calculated from (3). From a plot of versus , the saturation current values and follow from the slope and intersection of the plot, respectively. The values are listed in Table I. This table also lists measured values for the surface recombination velocity as determined from reverse bias current measurements [7]. The listed values and diffusion length were for the electron lifetime whereas the SRH lifetime followed from calculated from using . The results in Table I confirm the expectation that lowering the surface and bulk defect concentrations by pretreating the substrate will reduce surface recombination velocity and increase the recombination lifetimes and diffusion lengths.

Fig. 3. Ideality factor m versus the bias current IES plotted for accumulation (circle, VGS : V), depletion (square, VGS : V), and inversion (triangle, VGS : V) modes.

 03 5  +3 5

 01 0

C. Ideality Factor The ideality factor

is defined by the equation (9)

Taking the derivative results in (10) Since the dynamic resistance becomes value of

is defined as

, the (11)

and for each bias condition The measured values of are substituted into (11). The ideality factor versus the bias with the diodes operating in surface accumulation, current of 20 Hz is depletion, and inversion at a test frequency shown in Fig. 3. Unlike traditional methods which use DC to match curve-fitting techniques to extract a value for measured data over a wide current range, the values of shown in this figure were measured at individual bias points, to A. Note that thermal ranging from and that for the CZ no pretreatment significantly lowers wafer the measured values of depend on the surface charge state. D. Noise Measurements The schematic diagram for the noise measurement setup is the same as the ac measurement setup shown in Fig. 2. and The bias network sets the diode’s bias current . The small-signal equivalent circuit of the noise voltage measurement setup is shown in Fig. 4. In this figure, the is equal to . The current resistance spectral density of the equivalent bias resistor equals . The dynamic resistance and noise of

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Fig. 4. Small signal equivalent circuit with noise sources of the noise measurement setup.

(a)

(b)

Fig. 5. (a) Product f 1 Si; exc (f ) versus frequency f measured on a CZ no diode for (1) VES = 0:347 V, (2) VES = 0:306 V, and (3) VES = 0:266 V. (b) Same plot for a CZ IG diode for (1) VES = 0:377 V, (2) VES = 0:357 V, and (3) VES = 0:337 V. In both plots data obtained for surface accumulation (circle), depletion (square), and inversion (triangle) are displayed. 0

the diode are represented by and , respectively. The low-noise amplifier is modeled by an input resistance , noise generators and , and a and noise-free voltage gain . Both were measured prior to the device noise measurements. were In our experiment the values of , , and much greater than and the value of was much larger than . As a result (12) consists of a series combination The dynamic resistance of the dynamic resistance of the junction, denoted as , and . To exclude the effect of on the the bulk resistance noise, we derive (13) versus for the CZ no and CZ IG Plots of diodes are shown in Fig. 5(a) and (b), respectively, where . The curves in these figures show that the noise spectral density does not follow a pure 1/

dependence confirming that the dominant noise mechanism for this device is not Hooge-type diffusion noise. The diode noise measured on the CZ no wafer is a function of surface charge condition and is largest under surface accumulation. This is attributed to the presence of a strong surface noise component in accumulation of which the precise physical nature is presently unknown. Subsequent sections in this paper will focus on the diode noise measured in the surface inversion mode, which is assumed to represent bulk behavior. Even in the absence of mobility fluctuation noise, the Hooge parameter as calculated from can be used as a figure of merit to compare 1/ noise versus performance of different devices [4]. Plots of for both the CZ no and CZ IG diodes operating in accumulation, depletion, and inversion modes are shown in Fig. 6 for measured at Hz. This figure shows that the CZ IG diode has better performance than the CZ no diode indicating that intrinsic gettering reduces the sources of excess low frequency noise. Note that if 1/ Hooge-type noise was responsible for the observed phenomenon, the calculated values should have been independent of current. of both diodes measured at 10 The excess noise in Hz is plotted as a function of the gate bias voltage

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Fig. 6. Hooge parameter

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 12, DECEMBER 1998

 versus diffusion current IDif f .

3 Hz to 1 kHz experimental window used in our setup, the individual Lorentzians associated with the local noise sources distributed throughout the volume of the device need to be identified. In a linear noise analysis, the corner frequencies of these Lorentzian spectra and corresponding characteristic time constants are not affected by the position dependent transfer functions that describe the coupling of the local noise sources to the device terminals. Thus, by measuring and modeling these characteristic frequencies or time constants trap information can be derived. To explain the measured noise data, a three-level system is proposed as depicted in the insert of Fig. 8, where , , represent the electron and hole capture coefficients and , and emission coefficients, respectively. Other symbols have their usual meaning. Fig. 8 also displays the determining, noise spectrum shaping, electron trap lifetimes of the two and as a function of trap position. An bulk traps explanation for this graph will be presented below. Defect induced fluctuations in free carrier densities in the bulk SCR occur on a very short time scale and lead to subshot noise levels [9]. In the substrate these fluctuations would produce discrete Lorentzians. Consequently, this noise mechanism can not explain our experimental findings making it necessary . The rate to consider trap level occupancy fluctuations equation for such fluctuations is given by

(14) The electron capture coefficient can be modeled as , where is the electron capture cross section and is the electron mean thermal velocity equal to . and have much shorter time Since the fluctuations , both can be neglected in (14). The charconstants than , defined as the lifetime of electrons in the acteristic time trap states, becomes then

0 Fig. 7. Excess noise Si; (f ) versus gate bias voltage VGS measured at exc IES = 0:44 A. Insert: the excess noise Si;0 exc (f ) and G2m versus VGS 0 2 , for CZ no diode. The solid and dotted lines represent Si; (f ) and Gm exc respectively.

Fig. 7 for A. According to Hsu [8], surface noise , where . From the is proportional to , we conclude that insert of Fig. 7, showing the measured of the CZ no diode is correlated and scales only the , and thus is surface noise dominant in a limited range with of surface depletion mode operation. Apparently, the substrate pretreatments applied to the CZ IG sample eliminated the surface noise component. In the next section, the origin and location of the noise mechanism in the bulk region of the diodes will be discussed in detail. IV. DISCUSSION To determine the physical location and characteristics of the bulk defects responsible for the noise observed in the

(15) and are the electron and where hole Shockley densities, respectively, and which are position independent if trap activation energies are assumed to be constant. and are position dependent however, The values of and can be calculated from (16) and (17) , , and , are the quasi-Fermi levels where and the effective density of states for electrons and holes, respectively. The position dependence of the energy terms V together with the is illustrated in Fig. 9 for positions of the two, oxygen related independent trap states, eV and eV found from DLTS for the p-side of the n -p junction.

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the noise measurement corresponds to a 1.6 10 to 5.31 10 time window as indicated by the two arrows. This figure indicates that the defect centers located in a section of about 0.15 m wide at a distance of 0.06 m from the metallurgical junction on the p-side of the SCR are most likely responsible for the observed generation-recombination noise in the device. , now redefined as The values of (18)

Fig. 8. Characteristic time nt for trap levels ET 1 and ET 2 . The arrows on the time axis indicate the extent of the experimental time window. Insert: three-level system showing electron transitions.

and in the p-region coincide for most of the SCR, for dominates over the trap-dependent term and because and were assigned equal the capture coefficients of values in our calculation. To model the resulting current fluctuations in the diodes, we refer to the method proposed by Sah [10], where fluctuations cause fluctuations in in the trapped electron density and thus in the electrostatic potential the electric field difference across the bulk SCR, modulating the total diode current. According to Poisson’s equation

(19) Although acceptor-like trap behavior is assumed in (19), the final noise results apply equally well to donor-like traps due to the quadratic nature of spectral density. A fluctuation in at , denoted as , distributed in section , causes the electric field and the electrostatic potential to fluctuate by (20) and (21) , respectively [10]. Switching from density to for , where , the relation number fluctuations and becomes between (22)

Fig. 9. Energy band diagram of a n+ -p diode with only the p-side displayed.

Using To investigate whether the observed noise is caused by in Fig. 8), 2) hole 1) electron initiated transitions ( ), or 3) both electron and hole initiated transitions ( of all possible initiated transitions, the characteristic times and have been calculated with transitions involving cm . This value was reported for [6], and, due to lack of independent data, assumed for . , i.e., hole The calculations reveal that only for falls within the initiated transitions, the characteristic time low-frequency spectral window used in our measurements as V. illustrated in Fig. 8 for In this figure the metallurgical junction is located at and the negative and positive -values refer to the n - and p-region, respectively. The width of the SCR extends from 0 to 0.80 m. The 3 Hz to 1 kHz spectral window used during

(23) one derives via a Taylor expansion (24) Substituting (22) into (24) (25) which can be rewritten in terms of noise spectral densities as (26)

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(a) Fig. 10.

(b)

Measured and simulated current noise spectral densities versus frequency for (a) C26-1, CZ no diode and (b) ON28-7, CZ IG diode.

From generation-recombination noise theory it follows that (27) is the number of traps in the section considered, where and are the position dependent electron and hole and trap occupancy factors, given by

(28) and (29) Substituting (27) into (26) the final expression for the noise becomes produced by defects in section (30) for trap and for trap . The where , , and can be calculated using the values of position and bias dependent values of the energy levels. All , are known. The total device current variables, except noise spectral density, as observed at the terminals, follows from a linear summation of (30) over device volume. Matching the simulated with the measured excess noise spectra and assuming spatially homogeneous trap distributions results in 10 cm and 10 cm for the defect densities of 2 CZ no and CZ IG diodes, respectively. The noise stemming is negligible compared to the noise caused by . from is Thus, the trapping and detrapping of holes in trap state the most probable cause for the low-frequency noise observed. Note that the noise data confirm the presence of a defect lean zone in the CZ IG device. The simulated and measured spectral densities of the CZ no and CZ IG diodes are plotted in Fig. 10(a) and (b), respec. Good agreement is obtained tively, as a function of

Fig. 11. Individual noise spectral density components SI ; x due to the defects located in a section xj 1 A at a distance xj from the metallurgical junction in the p-region for the CZ IG diode biased at 0.337 V. The numbers in the figure refer to the subscript j in SI ; x . A summation of SI ; x over device volume results in the solid line labeled “Simulated.”

1

between simulated and experimental data both in terms of magnitude and spectral shape. To illustrate the noise contri, at distance butions stemming from individual sections from the metallurgical junction, the noise spectral density due to the defects in these sections and components given by (30), are plotted in Fig. 11 for the CZ IG diode is set to 0.01 m. biased at 0.337 V. In this example The dotted-line labels in the figure refer to the subscript in . For 0, 5, 10, and 15 solid lines are used to guide the eye. It is evident that the observed noise spectral density at this chosen bias condition is mostly due to traps located (at 0.05 m) and (at 0.15 m). The location between of the 3 Hz–1 kHz dominant noise source contributors at other

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Fig. 12. Location of the noise producing sections under different bias conditions for both CZ no and CZ IG diodes.

bias conditions for the CZ no and CZ IG diodes is displayed in Fig. 12. As the bias decreases, the values of and also decrease. Since is inversely proportional , will increase as the bias voltage and current to , associated with are lowered. Thus only values of traps, further away from the metallurgical junction will fit the spectral window. To explain the 1/ -like overall noise composition one needs inside the bulk SCR. The characteristic to realize that defined by (18) can then be simplified to time

(31) with

given by the depletion approximation as (32)

behaves as close to the These equations show that metallurgical junction where and are both constants. As , defined as the number of traps per a result, we find for unit time with a time constant between and

(33) which meets the McWhorter condition for 1/ noise. Both the simulated and the calculated current noise spectral densities versus the diode current are plotted in Fig. 13 at 20 dependence for , Hz. Although (30) seems to indicate an and terms reduce the bias voltage dependence of the and dependence for the CZ no and it to an overall CZ IG diodes, respectively, as confirmed by the experiment.

Fig. 13. Measured and simulated current noise spectral densities versus the diode current Idiode for both CZ no and CZ IG diodes at 20 Hz. The dashed lines are meant to guide the eye.

V. CONCLUSIONS The low-frequency 1/ -like noise of gated n p silicon diodes has been measured at room temperature as a function of emitter and gate bias voltage. The noise data are analyzed in terms of trapping and detrapping of holes in defect centers located in the bulk section of the space charge region at 0.43 eV below the conduction band. A characteristic time domain analysis reveals that this is the only process able to generate Lorentzian noise components within the 3 Hz to 1 kHz experimental window of the measurements. Both the trap characteristics and their precise physical location are resolved from the noise measurement showing that as emitter bias voltage increases, the noise producing SCR section moves closer to the metallurgical junction. Noise measurements independently confirm that appropriate thermal pretreatments lower the defect density in the active area of the diodes fabricated in Czochralski grown substrates. The defect centers are assumed to be associated with extended defect/oxide precipitate complexes. REFERENCES [1] E. Simoen, G. Bosman, J. Vanhellemont, and C. Claeys, “Impact of the substrate on the low-frequency noise of silicon n+ -p junction diodes,” Appl. Phys. Lett., vol. 66, pp. 2507–2509, May 1995. [2] F. N. Hooge, “1/f noise is no surface effect,” Phys. Lett., vol. 29A, pp. 139–141, 1969. [3] A. L. McWhorter, Semiconductor Surface Physics, R. H. Kingston, Ed. Philadelphia, PA: Univ. Pennsylvania Press, 1957. [4] A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986. [5] G. Bosman, “Charge transport and device parameters from noise measurement,” IEEE Trans. Electron Devices, vol. 41, pp. 2198–2204, 1994. [6] E. Simoen et al., “On the electrical activity of oxygen related extended defects in silicon,” Proc. Electrochem. Soc., vol. 94-10, pp. 670–683, 1994. [7] A. S. Grove and D. J. Fitzgerald, “Surface effects on p-n junctions: Characteristics of surface space-charge regions under nonequilibrium conditions,” Solid-State Electron., vol. 9, pp. 783–806, 1970. [8] S. T. Hsu, “Surface state related 1/f noise in p-n junctions,” Solid-State Electron., vol. 13, pp. 843–855, 1970.

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[9] K. M. van Vliet, “Noise and admittance of the generation-recombination current involving SRH centers in the space-charge region of junction devices,” IEEE Trans. Electron Devices, vol. ED-23, Nov. 1976. [10] C. T. Sah, “Theory of low-frequency generation noise in junction-gate field-effect transistors,” Proc. IEEE, vol. 52, pp. 795–814, July 1964.

Eddy Simoen, for a photograph and biography, see this issue, p. 2482

Jan Vanhellemont, photograph and biography not available at the time of publication. Fan-Chi Hou was born in Chia-Yi, Taiwan, R.O.C., on September 12, 1970. He received the B.S.E.E. and M.S. degrees in electrical engineering from the University of Florida, Gainesville, in December 1993 and August 1996, respectively. He is currently pursuing the Ph.D. degree in electrical engineering at the University of Florida. In January 1995, he joined the Noise Research Laboratory, Department of Electrical and Computer Engineering, University of Florida. His research has been on the characterization of low-frequency (LF) noise in silicon devices. He is currently focusing on analysis and implementation of LF diffusion and generation-recombination noise models in physics-based device simulators.

Gijs Bosman (M’82–SM’89) received the B.S., M.S., and Ph.D. degrees from the University of Utrecht, The Netherlands, in 1971, 1976, and 1981, respectively. In 1981, he joined the Department of Electrical and Computer Engineering, University of Florida, where he is a Professor and directs the Noise Research Laboratory. His research interests include the electrical noise and the charge transport properties of semiconductor devices and circuits. He has published more than 85 journal and conference papers on these topics. Dr. Bosman is a member of Tau Beta Pi and the American and Dutch Physical Societies.

Cor Claeys was born in Antwerp, Belgium. He received the electronics engineering degree in 1974 and the Ph.D. degree in 1979, both from the Katholieke Universiteit Leuven, Belgium. His doctoral research was in the field of processinduced defect characterization and gettering for VLSI technologies. From 1974 to 1984 he was, respectively, Research Assistant and Staff Member of the ESAT Laboratory of the Katholieke Universiteit Leuven, and has been a Professor there since 1990. In 1984, he joined the Interuniversity Micro-Electronics Center (IMEC), Leuven, as Head of the Silicon Processing Group. Since 1992, he is also responsible for Technology Business Development. His main interests are in general silicon technology including MOS, CCD, and CMOS-SOI, device physics including low temperature device operation, low-frequency noise phenomena and radiation effects, and defect engineering and material characterization. He has authored and co-authored three book chapters and more than 250 technical papers and conference contributions related to the above fields. Dr. Claeys is a member of the Electrochemical Society, SEMI, and the European Material Research Society.