An ultra low-power CMOS automatic action potential detector

346

IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 17, NO. 4, AUGUST 2009

An Ultra Low-Power CMOS Automatic Action Potential Detector Benoit Gosselin, Student Member, IEEE, and Mohamad Sawan, Fellow, IEEE

Abstract—We present a low-power complementary metal–oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18chip dissipates 780 nW, 2 . So it is suitable for massive and it features a size of 0.07 integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

mm

m

Index Terms—Biopotential detection, energy operator, neural recording, neuroprosthetics, ultra low-power circuits design.

I. INTRODUCTION

EUROSCIENCE research and neuroprosthetic devices require high-channel count microsystems to simultaneously record biopotential events from several neurons in the cortex. Efforts towards the development of fully implantable systems have led so far to the implementation of devices featuring up to a hundred recording channels [1], [2]. But, larger channel counts are required to address growing needs in this area. Implantable neural recording microsystems must operate at very low-power and be as little intrusive as possible to comply for safety. Moreover, a chronic usage of such devices prompts for wireless operation. Clearly, the main mechanism of information transmission in extracellular neural recording waveforms is a change in action potential (AP) generation rate by individual neurons. APs are weak amplitude signals

N

Manuscript received October 02, 2008; revised January 24, 2009; accepted March 10, 2009. First published April 10, 2009; current version published August 07, 2009. This work was supported in part by Natural Sciences and Engineering Research Council of Canada (NSERC), in part by the Canadian Research Chair on Smart Medical Devices, and in part by the Fonds Québécois de la Recherche sur la Nature et les Technologies (FQRNT). B. Gosselin is with the Polystim Neurotechnologies Laboratory, Electrical Engineering Department, École Polytechnique de Montréal, Montréal, QC H3C 3A7, Canada (e-mail: [email protected]). M. Sawan is with the Director of Polystim Neurotechnologies Laboratory, Electrical Engineering Department, École Polytechnique de Montréal, Montréal, QC H3C 3A7, Canada. Digital Object Identifier 10.1109/TNSRE.2009.2018103

) in the 100–10 kHz frequency band whose du(50–500 ration is of a few milliseconds. The rate of occurrence of APs varies from 10 to 120 occurrences per second [2]. The interest for automatic AP detection in neural recording implants is twofold. First, it allows for data reduction by processing only the relevant waveforms instead of the entire raw neural signal. Data reduction is essential in wireless neural recording devices because it decreases the data rate that must be handled by low-power telemetry. Secondly, because microelectrodes record APs from more than one neuron, reliable detection of waveforms is a necessary first step for the classification of multiunit biopotentials into single-units. The ability to distinguish between AP waveforms on a single channel allows assigning units to distinct neurons, for improving performances in neuroprosthetics applications in general [3]. Besides, several neuroscience investigations aim to understand the cooperative behavior of neurons and require well isolated units [4]. Integrated biopotential detectors have been proposed for real-time detection in multichannel devices [1], [2], [5]. However, most suggested designs are power hungry and present poor data integrity. In fact, they are merely able to capture a limited number of AP features, such as the time of occurrence or the peak amplitude. Harrison has suggested an analog detector which threshold is adjusted automatically according to the background noise characteristics [5]. Such detector only measures the portion of an AP that is higher than a positive threshold. Olsson has presented a digital threshold-based detector which sets the threshold value according to channel statistics [1]. It measures three distinct AP features to allow further discrimination. Other digital implementations of algorithms have been evaluated in [10], but those using several multiply and accumulate operations, such as the matched filter, may exceed the circuit area and power budget. Besides, detecting AP in an analog format enables for efficient channel and data management in further mixed-signal circuits (multiplexers, A/D converters, etc.), and digital back-end modules (controller, DSP, telemetry, etc.) as done in [9]. In addition, bursting, synchronous firing of neighboring neurons and electrode drift cause systematic variability in AP shapes [4], [11]. Present detectors are unable to capture such variability because they measure too few parameters. Using more AP features could lower the classification error rate by enabling fine processing, such as automatic sorting with a principal component technique. In general, the more features are available, the better the AP shapes can be distinguished. This paper presents a CMOS automatic detector for integral extraction of biopotentials in neural recordings. It achieves ultra-low-power and small size, so it can be integrated in several exemplary in a multichannel neural recording implant

1534-4320/$26.00 © 2009 IEEE

GOSSELIN AND SAWAN: AN ULTRA LOW-POWER CMOS AUTOMATIC ACTION POTENTIAL DETECTOR

Fig. 1. Block diagram of the automatic detection strategy. It is composed of a preprocessor, a decision block, and a time-delay element.

(one detector per channel) to handle several channels with modest overhead. Section II presents the detection algorithm. Section III presents its hardware implementation. Section IV presents the measured performance with the fabricated chip. Finally, conclusions on this work are drawn and strategies for massive integration of the proposed detector in a neural recording device are outlined in Section V. II. ACTION POTENTIAL DETECTION STRATEGY Fig. 1 depicts a block diagram of the proposed CMOS automatic detector. It comprises three main building blocks. First, a preprocessor emphasizes APs shapes and attenuates out-of-band noise. Secondly, a threshold function determines AP locations. Finally, a delay element provides delayed copies of detected APs to preserve waveforms integrity. A custom analog processor based on a mathematical energy operator is used for emphasizing the neural waveforms. Energy-based operators such as the instantaneous square of the signal, the absolute value operator, or the variance estimator are current operators in biopotential detection applications. The Teager energy operator (TEO) is one such energy-based operator that exhibits excellent sensitivity to transients and prompts for superior alignment of detected waveforms [12]. In addition, the TEO can suppress low-frequency artefacts such as ECG, respiration, and chewing noises, that can corrupt neural waveforms. A simulation, reported in Fig. 3, shows that the TEO successfully removes a large corrupting ECG waveform from a low-amplitude neural signal having very low-signal-to-noise ratio (SNR). Besides, its low complexity makes the TEO naturally suited for an analog implementation because it requires only a few circuit blocks. The TEO estimates the square of the instantaneous product of a signal amplitude and frequency. It is used as a time-frequency analyzer. Introduced in the foremost for discrete signal processing, the TEO algorithm has been according generalized to handle a continuous-time signal to (1) After preprocessing, the APs are passed through a threshold function to determine their locations. The threshold is applied to the preprocessed waveforms and the times of occurrence of APs are resolved upon threshold crossing. The threshold value must be set above the background activity level, and be optimized to

347

reduce detection errors. The threshold value can be taken as a scaled version of the TEO preprocessor average output [13]. Although not implemented in this design, adaptive adjustment of the threshold can be achieved by using a few additional analog building blocks (such as a lowpass filter) to assess the average output voltage of the preprocessor and use it to automatically set the detection threshold voltage in the decision block. As shown in Fig. 2, a time delay is induced for holding the original waveform, and ensuring that the portion of the AP happening before the threshold crossing point is not lost. As a result, the AP waveform integrity is preserved entirely. When used in a dedicated neural data acquisition chain, delayed copies of detected AP waveforms are promoted into the rest of the chain where they undergo sampling, digitization, etc. The time delay must be chosen equivalent to, or larger than the typical time elapsed between the onset of an AP and the detection point, so complete waveforms can be restored. In this work, we have emfrom real neural waveforms previously pirically determined recorded in the visual cortex of rats, and featuring high SNR. has been estimated to be around 600 , which is approximately 1/3 of a typical 2-ms AP duration. Fig. 2 illustrates the adopted AP detection strategy, and depicts waveforms encountered at the different processing stages in the detector. III. SYSTEM IMPLEMENTATION It is assumed that the input neural signal is sufficiently amplified from a few millivolt to a few hundreds of millivolt prior to detection, using a dedicated amplifier such as the one described in [14]. The detector is implemented using a novel custom analog processor made of three signal processing modules: a TEO preprocessor, a decision block, and a linear-phase delay filter. Each building block is based on ultra-low-power operational transconductance amplifier and capacitor (OTA-C) whose transistors are biased in the weak inversion regime. Subthreshold operation of MOS devices allows to achieve ultra-low power, and to operate in the very-low portion of the frequency spectrum (0–10 kHz), where lies most bioelectrical signals. A. Subthreshold OTA in MOSFETs is exponenThe subthreshold drain current tially related to the gate voltage. Moreover, the transconducof a weakly inverted MOS device is linearly related tance according to to (2) is the slope factor, and is the thermal voltage [14]. Currents on the order of 1 nA to a few tens of nA are used in the OTA building blocks employed both in the sizes. detector and in the delay filter to address power and However, operation at very low current comes at the cost of a reduced dynamic range (DR). Therefore, the OTA circuit chosen [Fig. 4(a)] incorporates source degeneration (SD) and bump linearization (BL) to simultaneously achieve low overall transconductances and better linear range [15]. SD is , implemented using diode connected nMOS devices in series with the sources of , , in the differential pair. The current flowing through the SD devices is converted into where

348

IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 17, NO. 4, AUGUST 2009

Fig. 2. Waveforms in the detector blocks. (1) Incoming AP waveform. (2) Enhanced AP. (3) Time window generated upon threshold crossing. (4) Time delay Td applied, so the detected AP is available from its onset.

the tanh-like characteristic of the subthreshold diff-pairs output ratios of the bump transistors must be chosen current. The ratios twice as that of the two outer arms devices in order to achieve maximal linearity [15]. An interesting fact , can be shown with BL is that appropriate sizing of to eliminate the third-order distortion terms in the diff-pair. Moreover, BL increases the amplifier linear range without increasing the noise [15]. Cascode transistors are used as well in the output stage to increase the amplifier output impedance and reduce loading effects when cascading building blocks. B. Mismatch and Process Variations

Fig. 3. Simulation for the TEO under a SNR of 0 dB with a low-frequency artifact. (a) Low-amplitude extracellular neural waveform corrupted with a large ECG artifact. (b) TEO removes most of the corrupting ECG.

a voltage that is fed back to the source of , to decrease . As a result, the overall transconductance of the their are decreased OTA is reduced as well. We can show that using SD, where . by a factor of This reduction in increases the linearity of the amplifier while it decreases the capacitor sizes needed. Unitary ratios are , and , . BL used in current mirrors formed by transistors are used as well to extend the linear operating range of the subthreshold OTA. The two series connected pMOS , in the central arm of the diff-pair are the devices bump transistors. These devices steal current from the two outer arms according to a bump-shaped function for linearizing

A problem with MOS transistors operating in weak inversion is the poor matching between devices. Mismatch causes random changes in the small drain current of MOSFETs, and thus in their . In this design, mismatch affects of amplifiers, and generates input-referred offset that can saturate some OTAs and render building blocks unfunctional. Mismatch can fortunately be reduced by means of adequate layout techniques such as interdigitated structures, and common-centroid configurations. Carefully matching MOS diff-pairs and current mirrors, distributing currents instead of voltages in the chip, and using local mirroring of currents have shown to enables for good performances in subthreshold filters [16], [17]. Moreover, a tuning strategy is recommended in [17] to reduce mismatch effects further and counter balance process variation in subthreshold filters. Since process variation affects devices of similar type by the same amount across the chip, the technique consists in are derived in tuning a single bias current from which all the circuits according to (2). This strategy is used along with matching and local mirroring in the design of our detector to achieve better tolerance to process variation and mismatch. C. Custom Energy-Based Analog Preprocessor A hardware implementation employing custom OTA-C analog circuits is used for the realization of the TEO pre-processor which block diagram is shown in Fig. 4(b). Its imple-

GOSSELIN AND SAWAN: AN ULTRA LOW-POWER CMOS AUTOMATIC ACTION POTENTIAL DETECTOR

349

Fig. 5. Simulated time responses of the differentiator to a step input.

Fig. 6. Simulated time response of the analog multiplier for a frequency doubling operation.

Fig. 5 presents the simulated time response of the differentiator. The circuit acts as a differentiator between 100 and 10 kHz, and it uses a 1-pf integrated capacitor. The subthreshold multiplier [Fig. 4(d)] uses a crossed-coupled quad structure in which a differential multiplication is obtained by driving the gates and bulks of four pMOS devices. This topology is compact and achieves higher input range than a CMOS implementation of the Gilbert multiplier [18], [19]. We can show that the difference output current of the bulk-driven multiplier simplifies to (4)

Fig. 4. Building blocks synthesizing the TEO-based preprocessor. (a) Subthreshold OTA with SD and BL devices. (b) Top-level diagram of the TEO preprocessor. (c) The differentiator circuit. (d) Four-quadrant analog multiplier, with V V -V and V V -V . All MOSFETs use W=L  =  unless otherwise stated. Annotated dimensions are in microns.

= 1 m1 m

=

=

mentation requires a differentiator, a four-quadrant multiplier, and a summing circuit. All three analog building blocks use the subthreshold OTA design described above. The differentiator [Fig. 4(c)] employs a three-OTAs configuration with one grounded capacitor [18]. Two differentiators are cascaded to implement the second-order derivative required by the TEO. This circuit subtracts a delayed version of the input signal from the input to approximate the time derivative. The differentiator transfer function is (3)

when the differential inputs are such that , and . The factor is the reciprocal of the slope in bulk CMOS processes). We have introfactor to extend the duced Source degeneration transistors linear range of the multiplier, and added input voltage level ) to ensure the source/bulk juncshifters (devices are reversed-bias. Fig. 6 presents the simutions in lated time response of the multiplier to a sine wave input, realizing a frequency doubling operation. The two-input terminals summing-circuit block [Fig. 4(b)] is based on two current summing OTAs directed towards a current-to-voltage con. This last building block sums the multipliers outverter puts to generate the final preprocessor output voltage, which is . D. Decision Block and Window Generation A low-power latched comparator and control circuits, whose schematic is shown in Fig. 7, implement the decision block. The comparator compares the output of the preprocessor with a

350

IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 17, NO. 4, AUGUST 2009

Fig. 7. Schematic of the decision block. The comparator output locks on VDD upon detection and stays asserted until it is reset by the timer, a short time later, for providing a suitable discrimination window.

predefined threshold voltage. When the measured signal , an AP is detected, and the comparator output is crosses asserted. The comparator includes a preamplifier stage for minimizing kickback noise, and a track-and-latch stage. A bias curprovides a suitable comparison speed of aprent of 20 nA in proximately 1 , and a simulated noise floor of 0.12 LSB, for an , on 8 bits. A gated signal (RST), input signal range of 200 generated using a 5-bit binary counter clocked at 16 kHz (signal CLK) and a few logic gates, enables the comparator to reset after 32 clock cycles following AP detection. When the count is done, the counter asserts (Fig. 7), which pulls RST low, and resets the latch. This generates a discrimination time window, which time length is equivalent to a typical AP duration (2 ms), during stays asserted. Thus, can which the comparator output be used to enable multiplexers, A/D converters, etc., to catch and digitize entire AP waveforms right at their onsets. When no AP is detected, the comparator resets at 16 kHz, so no AP occurrence is missed. E. High-Order Linear-Phase Filter Design A ninth-order linear-phase filter with a constant delay reto shift the sponse provides a suitable time delay AP waveform back to its onset upon threshold crossing. The signal delay (i.e., the group delay) provided by the filter is defined as the negative derivative of the phase angle, . Thus, the phase of the filter must change linearly with frequency over a prescribed bandwidth (i.e., the constant) to avoid distortion. The equiripple delay bandwidth, noted delay filter can achieve wider constant-delay bandwidth than other filter responses because it distributes the permitted delay error uniformly over the passband. However, this response does not have any close form transfer function, and its coefficients of an equiripple remust be obtained numerically. The sponse is approximated by (5) where is a normalizing frequency, and is the normalized is the inverse constant-delay bandwidth. We have that multiplied by a constant , that is of the desired delay , where is the intrinsic delay of the and are function of the filter equiripple filter. Constants order. Moreover, the filter uses an allpass transfer function because the presence of transmission zeros makes its delay twice as that of an all-pole filter of equal degree, which is such

Fig. 8. (a) Phase response and group delay of the equiripple filter. It exhibits a linear phase response within the prescribed bandwidth. (b) Ninth-order lineardelay filter based on a cascaded OTA-C structure [21].

. Tabulated values for a ninth-order that and equiripple filter with 5% delay error gives , which corresponds to a of 5.7 kHz, replacing (i.e., ) in , and using (5). This is well suited for this application because it contains most neural signal energy. Fig. 8(a) shows the ideal frequency and phase responses of the ninth-order equiripple filter whose coefficients were taken from tabulated values. Synthesising high-order filters requires particular attention to minimize circuit imperfections and parasitics because they present more sensitivity than lower-orders. Therefore, the selected filter topology uses a small amount of components and mitigates such effects. OTA-C filter topologies have shown excellent performances in low-power systems because they allow for high-order filter implementations with the least number of components. Low-power high-order OTA-C filters have already been used in medical applications [16], [17]. Equiripple delay filters have been implemented using OTA-C topologies as well -OTAs using small-size integrated [20]. Low-power, smallcapacitors and a cascaded topology are selected to implement the filter. The cascaded filter uses one first-order allpass section cascaded with four subsequent biquadratic allpass sections. The biquadratic sections are synthesized according to an allpass equal-capacitor-values topology, introduced in [21], and which yields a minimum number of components. Each biquad uses four OTAs and two equal-value capacitors to implement the required polynomial. The transfer function of one biquad section [Fig. 8(b)] is (6) where integer to 4. The filter coefficients are impleratios, whereas the capacitors scale the mented by OTA . The biquads use grounded capacitors and single-ended OTA [Fig. 4(a)] to minimize the parasitic poles that cause

GOSSELIN AND SAWAN: AN ULTRA LOW-POWER CMOS AUTOMATIC ACTION POTENTIAL DETECTOR

351

Fig. 9. Microphotograph of the fabricated chip. (a) Integrated TEO preprocessor and other constituting building blocks. (b) Integrated cascaded allpass delay filter.

excess phase shift, and to avoid the generation of parasitic zeros. Grounded capacitors absorb parasitic capacitances and need smaller area than floating ones. Small-geometry nMOS and pMOS devices are also used in the OTAs to minimise input and output parasitic capacitances. Moreover, cascode transistors increase the output impedance of the output stage. are individually adjusted by scaling the The subthreshold bias currents in the diff-pairs of each OTA, which currents are derived from one common low-current bias circuit. The whole ninth-order cascaded filter uses eighteen OTAs and nine 1-pf capacitors. The OTAs use bias currents ranging from 1.5 to 30 . nA to implement the required IV. EXPERIMENTAL RESULTS The proposed automatic detector was integrated in a TSMC six-metal one-poly CMOS process, and fits in an area 0.18. This represents 44% of the 400 400 of 272 257 per-channel-area allotment typically allocated for interfacing circuits in multichannel devices to match up with the pitch of a microelectrode array [1], [2], [14], [22]. We present typical results obtained with this integrated circuit, and statistical measurements from ten chips. A current generated externally from an adjustable resistor is used to derive internal biasing currents for all building blocks in the detector. So, each tested chip was tuned to compensate for process variations and mismatch, as discussed in Section III-B. A microphotograph of the integrated CMOS detector is presented in Fig. 9. Its building blocks, namely the preprocessor, the decision block, and the delay filter, dissipates 170, 250, and 356 nW, respectively, whereas the whole fabricated detector dissipates 776 nW. This corresponds to less than 10% of the typical power consumption achieved by lately reported dedicated first-rank amplifiers (see [22] for a review; one such amplifier per channel must be used in any neural recording device). A synthetic neural signal presenting a realistic firing rate was constructed and used as an input signal for testing the automatic detector. The signal, presenting a SNR of 6 dB, was uploaded in a SR785 Dynamic Signal Analyzer (Stanford Research Systems, Sunnyvale, CA),

Fig. 10. Measured output of the detector. (a) Synthetic input signal (top). TEO preprocessor output (second trace). Delayed waveforms at the filter output (third trace). Windows generated by the decision block (bottom). (b) Closer view on detected waveforms with a measured delay close to 600 s.

and played at the detector input. Fig. 10(a) presents the detector output response to the synthetic signal. As seen, the multiple APs embedded in the background noise (top trace) are successfully detected and isolated by the detector when the TEO output (second trace) crosses the detection threshold. The threshold voltage is generated off chip and is adjusted manually with a tunable voltage reference. The linear-phase filter was adjusted by tuning the bias current until it yields a signal delay of (third trace). Discrimination windows of proper exactly 600 lengths are generated upon threshold crossing (bottom trace). The generated windows lengths can be adjusted by varying the frequency of the 5-bit timer for delimiting the detected APs adequately. Fig. 10(b) shows a delayed waveform measured at the output of the equiripple delay filter. The measured delay for

352

IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 17, NO. 4, AUGUST 2009

tected neural waveforms with a delay element implemented by means of a continuous-time linear-phase filter. In fact, our prior work as shown that the power spent per channel in lately reported integrated multichannel microsystems ranges in the hundred of microwatts [22]. Our integrated detector requires less than 1% of this power budget and it fits well within the area allotment typically allowed, as discuss in Section IV. Moreover, a multichannel device (see [22] for a suggested integration approach) using one such detector per channel would have room for the inclusion of other circuits (amplifiers, filters, etc.). For example, integrating the proposed detector along with the first rank amplifier presented in [14] to form a practical recording , which channel would require a chip area of around 0.12 is well within the budget discussed. Thus, the presented circuit is suitable for implementing scalable neural recording channels of various types, and does not represent a bottleneck for channel expansion. Besides, our analog detector can be used in a channel management strategy, as suggested in the Section I. Its output provides the control signal required to dynamically activate/deactivate mixed-signal circuits and digital back-end modules in a neural implant right upon detection of neural events. Such architecture would benefit on the very low-duty cycle of neural signals, and allow most building blocks to remain in an idle state between APs, draining very low power.

TABLE I PERFORMANCES OF THE INTEGRATED DELAY FILTER

TABLE II CHARACTERISTICS OF REPORTED INTEGRATED NEURAL DETECTOR

this chip was 592 . As seen, the waveform is slightly amplified by the filter, but not distorted. The filters typically achieve a total harmonic distortion (THD) smaller than 1.2% within an input range of 40 mVpp. The typical phase response measured within the integrated delay filters presents a total phase shift of around 1.4 kdeg near 6 kHz, which is in accordance with was measured Fig. 8(a). An average signal delay of within the ten chips for equivalent bias currents without fine tuning. This signal delay represents about 1/3 of a typical AP , and duration, as targeted. Moreover a gain of of were obtained across the 10 integrated a filters. Table I summarizes the characteristics of the integrated delay-filter. The simulated performances were obtained from Monte Carlo trials. A figure of merit (FOM) has been defined [17] to assess and compare the performances of low-power filters. The FOM is expressed as (7) where DR is the dynamic range, is the number of pole plus zeros, and , the center frequency for which the result is reported. The FOM achieved with the cascaded allpass filter is , which is clearly within best reported results acof 3.5 cording to [17]. Table II compares our presented work with previously reported integrated detectors. Our detector is the only one to offer small-size, low-power, and full waveform integrity altogether. V. CONCLUSION We have presented a submicrowatt automatic AP detector that employs a custom analog implementation for use in multichannel neural recording implants. It is based on the TEO, an energy-based operator. The detector improves the integrity of de-

ACKNOWLEDGMENT The authors acknowledge the design and testing tools provided by CMC Microsystems (Kingston, ON, Canada). REFERENCES [1] R. H. Olsson, III and K. D. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2796–2804, Dec. 2005. [2] R. R. Harrison, “A low-power integrated circuit for a wireless 100Electrode neural recording system,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 123–133, Jan. 2007. [3] F. Wood, M. J. Black, C. Vargas-Irwin, M. Fellows, and J. P. Donoghue, “On the variability of manual spike sorting,” IEEE Trans. Biomed. Eng., vol. 51, no. 6, pp. 912–918, Jun. 2004. [4] K. D. Harris, D. A. Henze, J. Csicsvari, H. Hirase, and G. Buzsaki, “Accuracy of tetrode spike separation as determined by simultaneous intracellular and extracellular measurements,” J. Neurophysiol., vol. 84, pp. 401–14, Jul. 2000. [5] R. R. Harrison, “A low-power integrated circuit for adaptive detection of action potentials in noisy signals,” in Proc. 25th Annu. Int. Conf. IEEE Eng. Med. Biol. Soc., Sep. 2003, vol. 4, pp. 3325–3328. [6] T. Horiuchi, T. Swindell, D. Sander, and P. Abshier, “A low-power CMOS neural amplifier with amplitude measurements for spike sorting,” in Proc. 2004 Int. Symp. Circuits Syst., May 2004, pp. 29–32. [7] C. L. Rogers and J. G. Harris, “A low-power analog spike detector for extracellular neural recordings,” in Proc. 2004 11th IEEE Int. Conf. Electron., Circuits Syst., Dec. 2004, pp. 290–293. [8] A. M. Haas, M. H. Cohen, and P. A. Abshire, “Real-time variance based template matching spike sorting system,” in 2007 IEEE/NIH Life Sci. Syst. Appl. Workshop, 2007, pp. 104–107. [9] A. M. Sodagar, K. D. Wise, and K. Najafi, “A fully integrated mixed-signal neural processor for implantable multichannel cortical recording,” IEEE Trans. Biomed. Eng., vol. 54, no. 6, pp. 1075–1088, Jun. 2007. [10] I. Obeid and P. D. Wolf, “Evaluation of spike-detection algorithms for a brain-machine interface application,” IEEE Trans. Biomed. Eng., vol. 51, no. 6, pp. 905–911, Jun. 2004. [11] M. S. Fee, P. P. Mitra, and D. Kleinfeld, “Variability of extracellular spike waveforms of cortical neurons,” J. Neurophysiol., vol. 76, pp. 3823–3833, 1996.

GOSSELIN AND SAWAN: AN ULTRA LOW-POWER CMOS AUTOMATIC ACTION POTENTIAL DETECTOR

[12] C. J. Hwan, J. H. Kyung, and K. Taejeong, “A new action potential detector using the MTEO and its effects on spike sorting systems at low signal-to-noise ratios,” IEEE Trans. Biomed. Eng., vol. 53, no. 4, pp. 738–746, Apr. 2006. [13] S. Mukhopadhyay and G. C. Ray, “A new interpretation of nonlinear energy operator and its efficacy in spike detection,” IEEE Trans. Biomed. Eng., vol. 45, no. 2, pp. 180–187, Feb. 1998. [14] B. Gosselin, M. Sawan, and C. A. Chapman, “A low-power integrated bioamplifier with active low-frequency suppression,” IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 3, pp. 184–192, Sep. 2007. [15] R. Sarpeshkar, R. F. Lyon, and C. Mead, “A low-power wide-linearrange transconductance amplifier,” Analog Integrated Circuits Signal Process., vol. 13, pp. 123–151, 1997. [16] R. Sarpeshkar et al., “An ultra-low-power programmable analog bionic ear processor,” IEEE Trans. Biomed. Eng., vol. 52, no. 4, pp. 711–727, Apr. 2005. [17] P. Corbishley and E. Rodriguez-Villegas, “A nanopower bandpass filter for detection of an acoustic signal in a wearable breathing detector,” IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 3, pp. 163–171, Sep. 2007. [18] C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison Wesley, 1989. [19] G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: A tutorial,” IEEE Trans. Circ. Syst. II, vol. 45, no. 12, pp. 1550–1563, Dec. 1998. [20] S. Dosho, T. Morie, and H. Fujiyama, “A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25- CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 559–565, May 2002. [21] C. Chun-Ming, H. Chun-Li, C. Wen-Yaw, H. Jiun-Wei, and T. Chu-Kuei, “Analytical synthesis of high-order single-ended-input OTA-grounded C all-pass and band-reject filter structures,” IEEE Trans. Circuits Syst. I, vol. 53, no. 3, pp. 489–498, Mar. 2006. [22] B. Gosselin et al., “A mixed-signal multi-chip neural recording interface with bandwidth reduction,” IEEE Trans. Biomed. Circuits Syst., vol. 3, pp. 129–141, 2009.

m

353

Benoit Gosselin (S’02) received the B.Sc. degree in electrical engineering from École Polytechnique de Montréal, Montréal, QC, Canada, in 2001. He is currently working toward the Ph.D. degree in microelectronics under the direction of Prof. M. Sawan. His thesis topic involves the design and implementation of low-power neural integrated interfaces and he is interested in low-noise amplifiers, low-power circuit techniques and biotelemetry.

Mohamad Sawan (S’88–M’89–SM’96–F’04) received the Ph.D. degree in electrical engineering from the Université de Sherbrooke, Sherbrooke, QC, Canada, in 1990. He joined Ecole Polytechnique de Montréal in 1991, where he is currently a Professor in microelectronics and biomedical engineering. His scientific interests are the design and test of mixed-signal circuits and systems, digital and analog signal processing, modeling, integration, and assembly. He holds the Canada Research Chair in Smart Medical Devices, and he is leading the Microsystems Strategic Alliance of Quebec (ReSMiQ). He is Editor of the Mixed-Signal Letters. Dr. Sawan received the Barbara Turnbull 2003 Award for spinal cord research, the Medal of Merit from the President of Lebanon, the Bombardier Medal of Merit from the French Canadian Association for the Advancement of Sciences, and the American University of Science and Technology Medal of Merit. He is Associate Editor of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS. He is fellow the Canadian Academy of Engineering, and the Engineering Institutes of Canada. He is also “Officer” of the National Order of Quebec.