An ultra-low-p c

An ultra-low-ppower front-end for diffferential c capacitive sensors Patcharee Kongppark, Frederick Mailly, Laurent Latorre, Pascal Nouet N C – LIRMM 161, Rue Ada – 34095 Montpellier Cedex C 5 - France University of Montpellier / CNRS Abstract- In this paper, we present a sim mple, compact and low-power interface for differential capaccitive sensors with direct digital output. The complete system is i composed with a current to voltage amplifier, an integrator, a comparator and a feedback capacitor connected in parallel with w one of the two capacitances. Overall a Sigma-Delta mod dulator is obtained that is able to deliver directly a bit stream proportional p to the differential capacitance.

converter. The proposed circuit (Fig.1) ( consists of two cascode current mirrors connected togetther to form an I/V converter with very high output impedannce. The output node of the capacitive bridge is connectedd to the self-biased and low impedance input VG. The outputt voltage Vout is then integrated with a time constant adjusted by b the output resistance rout of the I/V converter and the load caapacitance CL.

INTRODUCTION

I.

The Active Bridge was initially proposedd and patented [1] for conditioning low-power resistive sensors as an alternative to the classical Wheatstone bridge. Among advantages of this bridge, it is worth noting that: • It is a self-biased trans-resistance ampllifier, i.e. a current to voltage converter that does not requirre a biasing stage. • It exhibits a very large output resistannce that can reach several GΩ. • It is very compact and easy to design. In this work, we extend the use of this briidge to differential capacitive sensors. The idea is to convert a difference d between two capacitances in a small current thhat will then be transformed in a voltage and integrated. Com mparing this output signal with a reference voltage is then used to build a closedloop system where a constant capacitance is suitably placed in parallel with one of the capacitor to coompensate for the mismatch between both sensing capacitancee. The so-obtained system is known as a ΣΔ modulator wherre a direct one-bit digital output is obtained. The output bit stream is then a representation of the differential capacitance. In the following sections, we first present the t principle of the proposed measurement architecture and theen the design of a first prototype that has been validated using electrical simulations to determine overall performances of the proposed front-end. DIFFERENTIAL CAPACITIVE SENSING

II.

A.

Principle

For a differential capacitive sensor, the symmetrical capacitance variations can be easily conveerted in an output current IC using a capacitive bridge and AC voltage sources in phase opposition. Therefore, to measure annd amplify the IC current, this paper presents a modificatioon of the Active Bridge to obtain a compact and low-power current-to-voltage

Fig. 1 Differential Capacitance-to-Volltage converter topology based on a modified Acttive Bridge

B.

Design of the Capacitannce to Voltage Converter

To demonstrate low-powerr ability, a total current consumption of 2µA (i.e. 1µA per branch) has been chosen for the I/V converter under a 3.3V V supply voltage. In order to meet this power constraint and to set the biasing point of VG and Vout to about VDD/2, (VGS - VT)NMOS and (VGS - VT)PMOS are set to 0.325V and 0.125V respectively. Moreover, PMOS and NMOS transistors with large arreas are used to decrease the flicker noise’s corner frequency. For a given variation of the meeasurement capacitors, ΔC, the output signal must be studied duuring two independent phases: Φ1, where slopes of and are positive and negative respectively and Φ2 where slopes s are reversed (Fig.2). Generation of triangular-wave siignals in phase opposition, and , is not discussed in thhis paper. During each phase, input current IC is constant becaause and are constant and the resulting input and outpuut signals are then square wave

signals given by:

modulator. Finally, the ΔC valuue is given for each phase by the ratio of ‘1’ in the output bitsttream as illustrated in figure 4. (1) (2) (3)

2∆ 2∆ 2∆ //

,

|

//

|

In order to keep a correct biasing of the inpput stage of the I/V converter, the square wave input current IC has h to be limited to around 1/1000 of the bias current of the bridge b branch (i.e. 1µA/1000=1nA) for the full range of ΔC.. Therefore, for a targeted full range of ±5pF (i.e. ±5% of thhe nominal value), amplitude and frequency of and are fixed f to 5V and 10 Hz respectively. Indeed, a sensor with low l bandwidth is considered in this preliminary study. Sincee the square wave signal is amplitude modulated by the capaccitance variations, the frequency of and should be incrreased for sensors with higher bandwidth.

o the ΣΔ modulator Fig. 3 Block diagram of 52.5 52

Ratio of 1(%)

Where

51.5 51 50.5

Φ1 Φ2

50 49.5 49 48.5 48

Vin

47.5 -0.2

V Vout

Φ1 Φ2 Φ1 Φ2 Fig. 2 Input and output signals in absence of loaad capacitance

IMPLEMENTATION IN A FIRST-ORDER ΣΔ Δ MODULATOR A.

Principle

The principle is to measure the amplitude of o the square wave input current by performing an analog-to-ddigital conversion during each phase Φ1 and Φ2. Then, the twoo digital values are subtracted to obtained the digital output. Due to its high resolution and its ability to convert analoog output signals resulting from sensor with low bandwidthss, a ΣΔ modulator architecture is chosen to implement this AD DC. Block diagram of the complete architecture is given in figuure 3. For a given ΔC, the input signal of the modulator iss a difference of capacitance C1-C2 = 2ΔC. Therefore, the 1-bit DAC of the feedback is realized using a capacitance Cfb which is added in parallel to C1 or C2 according to the D-typpe flip-flop output. During each phase, Φ1 and Φ2, positive annd negative current impulsions induced by the commutation of o Cfb are used to cancel the average value of the I/V connverter output by comparing the integrated output voltage Vout to a voltage reference that must be more or less in the raange of VDD/2. The comparator output is then sampled at thee modulator clock frequency fclk and the feedback capacitor is switched according to the comparator output level. Note that thhe logic control of the DAC has to be inverted when switchinng from Φ1 to Φ2 since the sign of the C/I converter is diffferent (due to the inversion of the slopes of and ). In I order to reach accurate operation, the ΣΔ modulator needs to be clocked at a much higher frequency than the frequencyy fin of the input signals and and then, than the cappacitance variation ΔC. Moreover, the cut-off frequency fc of the I/V converter has to be set much lower than fclk, to obbtain the pseudointegrator behavior necessary for a proper functioning of the

-0.1

-0.05

0 0.05 ∆C C/C (%)

0.1

0.15

0.2

Fig. 4 Modulator output (i.e. ratio of ‘11’ in the output bitstream) vs. relative variation of sensinng capacitances

B. III.

-0.15

Implementation

Fig. 5 presents the transistorss-level implementation of the ΣΔ modulator using a 0.35µ µm technology from Austria MicroSystem. The integrator is implemented as a simple low pass filter composed of the highh output resistance of the I/V converter (73GΩ) and a load caapacitance CL (500fF) [2]. The resulting cutoff frequency fc is about 4 Hz. The sampled comparator block is a standard AMS block (COMP01B) and the clock frequency fclk is set too 10 kHz to control a standard cell from the foundry used as a Flip-Flop. During Φ1, when the Flip-Flop output is high, S0 is closed and S1 is opened. During Φ2, logic control is inverted: i when the Flip-Flop output is high, S1 is closed and S0 is opened.

Fig. 5 Implementation of the complete readout r architecture with direct digital output: a ΣΔ moduulator topology

This non-linear phenomenon is clearly visible in figure 7 where the modulator offset of -4% is also observed.

A.

Dead bands and dithering

The full scale, FS, of a sensor is generally defined to be the maximum value that must be measured; in our case a given ΔC/C (in %). The modulator output is the difference between the ratios of ‘1’ (in %) in the output bitstream during Φ2 and Φ1 phases. The modulator gain is then given in %/% (i.e. difference of percentage of ‘1’ per percentage of variation of the sensing capacitances). Using these assumptions, the feedback capacitance and the modulator ideal gain are respectively: 2 . 100 100

(4) (5)

Fig. 6 presents modulator output as a function of ΔC/C (%) for transient simulations with and without electronic noise. Values of C, Cfb, FS and ideal modulator gain are 100pF, 10pF, 5% and 20 (%/% will be omitted from now) respectively. For each phase, the ratio of ‘1’ is estimated on 500 clock periods using a transient analysis (black square) and a transient noise analysis (grey circle). As expected for a first order modulator, a large dead band is observed in the vicinity of ΔC/C=0% when noise-induced dithering is not taken into account. Fortunately, electronic noise is large enough to suppress this dead band in the transient noise analysis. The resulting gain and offset, evaluated over a ΔC/C range of ±0.5% (Fig. 6-top), are respectively equal to 19.7 and -4%. This gain is very close to the ideal gain of 20. Over the full scale (Fig. 6-bottom), the average value of the simulated modulator gain is equal to 19.3. This smaller value is due to the gain saturation that is commonly observed close to FS and is related to noise dithering effect [3].

4.00

10 0

2.00 0.00 -2.00 -4.00 -6.00 -8.00 -5

B.

-1

∆C/C (%)

1

3

5

Impact of variability

To study the impact of manufacturing variability we have conducted a set of Monte Carlo simulations using both process (wafer to wafer) and mismatch (intra die) variations for the previous values of C, Cfb, FS and ideal gain (i.e. 100pF, 10pF, 5% and 20 respectively). Results are extracted from transient noise analysis for 100 simulations and both offset and gain has been analyzed. Output offset is typically lower than 10% of the full range (Fig. 8.a). Therefore, it could be easily integrated in the measured capacitance range by increasing proportionally the feedback capacitance. Concerning the scale factor, variations are very small (Fig. 8.b). This is obviously due to the closed-loop architecture of the modulator and to the fact that the scale factor depends on a ratio of capacitances (C/Cfb) that is not affected by process variations but only by mismatches with a standard deviation of about 1%. 25 20

20

18

18

17

15

13

10

7

5

3

2

1

y = 19,7x - 4

-10

-3

Fig. 7 Deviation of modulator output from ideal output (i.e. offset null and ideal gain of 20) vs. relative variation of capacitor

number of circuits

Ratio of 1 Φ2 - Φ1 (%)

20

6.00

Error (%)

SIMULATION RESULTS

IV.

1

0 -10

-20 -0.5

-0.3

-0.1 0.1 ∆C/C (%)

0.3

0.5

-8

-6

-4

0 2 4 6 9 10 Offset a) Output Offset (i.e. difference of ratios of ‘1’ (in %) for ΔC/C=0%) 30

100 80 60 40 20 0 -20 -40 -60 -80 -100

number of circuits

Ratio of 1 Φ2 - Φ1 (%)

gain: 19.3

27

25 20

-2

25

21 15

15 9

10

3

5 0

-5

-3

-1

∆C/C (%)

1

3

Fig. 6 Modulator digital output vs. relative variation of capacitor

5

19

19.33

19.67 20 20.33 20.67 Gain b) Scale factor of the modulator in the range ΔC/C=± 0.3% Fig. 8 Monte Carlo Simulations (100 runs)

Full-scale and sensor adaptability

A nominal sensing capacitance of 100pF may appear too large for most MEMS applications; therefore, adaptability was studied in particular for smaller nominal capacitance. Moreover, to improve the input Signal to Noise Ratio (SNR), frequency of and has been increased up to 100Hz. Since a ΣΔ modulator operates in closed-loop architecture, both full-scale and gain are only fixed by the feedback capacitance. Fig. 9 presents simulated outputs of the modulator for different nominal capacitances (100, 10 and 1pF) and different full-scales (1, 5 and 10%). For 100pF and 10pF, obtained scale factors are close to ideal gains (i.e. 100/FS) even if an increasing discrepancy is observed when nominal capacitance and FS are decreasing. Then, for 1pF, a modulator malfunction is finally observed for the smaller FS (1%).

1.8

4 3.5

1.75

100 80 60 40 20 0 -20 -40 -60 -80 -100

analog voltage (V)

Ratio of 1 Φ2 - Φ1 (%)

y = 95.22x - 0.181

y = 9.910x - 0.363 y = 19.35x - 3.669 1% 5% 10% -10

100 80 60 40 20 0 -20 -40 -60 -80 -100

-5

0 ΔC/C (%) a) C = 100pF

5

3

1.7

2.5

1.65

2 1.5

1.6

1

1.55

0.5

1.5

0

1.45

-0.5 0.03

10

0.032

0.034 0.036 time (s)

0.038

0.04

Fig. 10 I/V converter output (in blue), voltage reference of the comparator (in red) and modulator digital output (in black)

y = 92.66x + 2.181

Ratio of 1 Φ2 - Φ1 (%)

y = 17.69x + 2

1% 5% 10%

100 80 60 40 20 0 -20 -40 -60 -80 -100

-5

0 ΔC/C (%) b) C = 10pF

CONCLUSION

V. y = 9.522x - 0.181

-10

Ratio of 1 Φ2 - Φ1 (%)

The observed malfunction relates to a poor SNR at the comparator input where the flicker noise of the I/V converter is too high to be compensated by the feedback capacitor. Therefore, the comparator output is mainly governed by the input 1/f noise and the modulator output may be transiently blocked to ‘0’ or ‘1’, leading to an erroneous digital output (Fig. 10). To reduce the impact of this noise, the I/V converter should be re-designed to improve the input SNR, for example, by increasing the transistors’ area to decrease their noise or/and by increasing the input resistance to increase the input voltage (see formula 2). Another solution would be to increase the input frequency to increase both and but clock frequency fclk should be increased in the same proportions to maintain the digital output resolution.

digital output (V)

C.

5

10

y = 40.54x + 39.52

In this paper, we have introduced new compact readout architecture for differential capacitive sensors. Most important advantages of this front-end are i) the comprehensive architecture where the scale factor depends only on a ratio of capacitances, ii) the small number of components thus allowing low-power operation and multi-channel devices, iii) the scalability of the front-end for different range of capacitance and iv) last but not least, the direct digital output. The operation has been demonstrated thanks to electrical simulations over a large range of capacitance and full scales. Silicon validation and full integration on an ASIC are currently under investigation. REFERENCES [1]

y = 9.266x + 2.181

y = 17.4x + 6

1% 5% 10% -10

-5

0 ΔC/C (%) c) C = 1pF

5

[2] 10

Fig. 9 Modulator output for different nominal capacitances (a) C = 100pF, (b) C = 10pF, (c) C = 1pF and different full scales (1, 5 and 10%)

[3]

E. M. Boujamaa, P. Nouet, F. Mailly, L. Latorre, Circuit for Amplifying a Signal Representing a Variation in Resistance of a Variable Resistance and Corresponding Sensor, US Patent 8,487,701 B2, July 16, 2013. Hacine S., Mailly F., Norbert D., Latorre L., Nouet P. « An ultra low power temperature sensor for smart packaging monitoring Compensation » IEEE Design, Test, Integration and Packaging of MEMS or MOEMS (DTIP'2011),May 2011. O. Leman, PhD dissertation, Montpellier University, September 2009.