An efficient channel segmentation approach for a large-signal NQS MOSFET model

An efficient channel segmentation approach for a large-signal NQS MOSFET model

Matthias Bucher a Antonios Bazigos b a Technical b National

University of Crete, 73100 Chania, Greece

Technical University of Athens, 15780 Athens, Greece

Abstract This paper presents an efficient formulation of a channel segmentation based approach to non quasi-static modelling of the MOS transistor, in the context of a charge-based MOSFET model. In this minimal channel segmentation approach, only the essential charge equations are evaluated for each channel segment while other effects are handled at device level. As a result, simulation time is drastically reduced compared to a full channel segmentation approach. The model is validated versus measurement up to 10GHz and passes relevant benchmark tests. Key words: Channel Segmentation, non quasi-static, compact MOSFET model, EKV.

1

Introduction

The computational complexity of compact models is an important issue for the design of high-speed electronic circuits. The recent advent of new charge-based and surface potential based compact MOSFET models has revived the debate for the efficiency of different compact models. The present work examines some

Preprint submitted to Elsevier

14 August 2007

of the efficiency issues related to non quasi-static (NQS) effect modelling in MOSFETs. The quasi-static (QS) assumption in MOSFETs, according to which charges respond instantly to changes of the potentials at the terminals, becomes invalid at higher frequencies. The critical frequency at which this NQS behaviour becomes important is inversely proportional to the square of the gate length and is also a function of bias e.g. [1,2]. Several approaches have been developed to model NQS behaviour. One is to use complex frequency-dependent transadmittances and admittances providing a small-signal NQS model [1,2]. The only drawback of this approach is that it is not applicable to time-domain (or large-signal) analysis. Another approach, called channel segmentation, is to replace the MOSFET with more than one shorter MOSFETs in series with equal total gate length e.g. [3]. The spline collocation-based NQS model [4] has a reduced computational burden with respect to channel segmentation but also requires the definition of additional nodes. These two approaches provide consistent small- and large-signal NQS models. In the present work, the ‘minimal’ channel segmentation approach is introduced, in the context of the EKV3 charge-based model, and its accuracy and computational cost are examined with respect to full channel segmentation.

2

Charge-based model structure

The EKV3 compact MOSFET model is based on the charge-sheet theory. Before moving to the discussion about the channel segmentation, the basics 2

of the charge-sheet model theory will be shortly reviewed. Without loss of generality, only the part of the model that describes the drain current shall be discussed. The formulation could be simplified to the following. Pinch-off voltage (VP ) is the potential that, if applied at the surface of the channel, will make an inversion layer just start to appear [6]. Pinch-off voltage mainly depends on the gate to bulk potential and may be expressed as:

VGB − VT O VP ∼ = n

(1)

where VT O is the threshold voltage at VSB = 0 and n is a slope factor that has a small dependence on VG . Typically, n has a value between 1.4 and 1.1, depending on the bias and the geometry of the device. The normalized inversion charges at source and drain (qs and qd respectively) may be calculated according to the difference between VP and VSB and VDB , respectively.

qs = F −1



VP − VSB VP − VDB , qd = F −1 UT UT F (q) = 2q + ln q 





(2)

Here, UT is the thermal potential, which is the normalization factor of the potentials, within the formulation of the model. Specific current (ISP EC ), on the other hand, is the normalization factor for the currents. Mainly the process parameters and device geometry affect the nominal value of ISP EC . 3

ISP EC = 2 · n · UT2 · µ · COX ·

W L

(3)

Here, µ is the carrier mobility, COX the oxide capacitance per unit area and W and L are the effective width and the length of the channel. Finally, the drain current is given by the following equation:



IDS = ISP EC · qs2 + qs − qd2 − qd



(4)

A more detailed description of the above can be found in [1,2,5–7]. The above equations for inversion charge (2) and drain current (4) may be considered as the core of a MOSFET model that has only two parameters, VP and ISP EC , and two inputs, source and drain potentials. This core model produces the drain current according to the source and drain potential, see Figure 1(a). The rest of the model is responsible for describing all the higher-order effects. The EKV3 model includes extensions that cover all the phenomena that appear in modern CMOS technologies [5]. For example, due to the vertical field in the channel, the effective mobility, and consequently the specific current of the device, is affected by the gate bias. By modifying adequately ISP EC , according to gate bias, and by feeding the core model with the effective specific current, the model can be extended to cover this effect. Another example is the part of the model that deals with the drain induced barrier lowering effect and calculates how the pinch-off voltage is affected by source and drain biases, mainly at short channel devices. Yet another example are the equations of the model that calculate the effective drain potential due to velocity satu4

ration. This list of examples may be extended to cover all of the higher-order phenomena [8]. Macroscopically, this part of the model takes as input the geometry of the device and the potentials at the nodes, and feeds the core model with the effective values that it needs as input, see Figure 1(b). Note that the core charge model equations actually are a minor portion of the overall computational effort. The above description of model structure, while it is based on the charge-based EKV model, may be applicable to any other compact model with a similar hierarchical division.

3

Efficient Channel Segmentation

The main motivation to adopt a channel segmentation scheme is to provide a large-signal NQS model consistent with the small-signal analysis. However, when segmenting the MOSFET channel into shorter parts, nodes are introduced between each channel segment increasing the computational effort. The number of segments should be selected in a suitable trade-off among accuracy and speed. Furthermore, a channel-segmented transistor should have the same static behaviour as a single-channel transistor to ensure consistency among QS and NQS models. Both these aspects will be examined in dedicated sections below. Extra attention should be paid to how the shorter transistors are modeled. Each segment is a shorter part of the entire channel and not a shorter transistor. Extrinsic elements, such as series external resistors and overlap/fringing capacitances, are naturally placed only at the ends of the whole device and 5

not between the segments of the channel. On the other hand, the length related parameters need to be scaled down, according to the shorter length of the segments. The novelty of the minimal channel segmentation approach resides in the hierarchical breakdown among the effects that may be treated at device level for the entire channel, and the part of the model that must be treated locally for each segment of the channel. Figure 1(c) explains the model structure of the EKV3 NQS model. In this approach, only the basic charge equations are evaluated for each segment of the channel. The higher-order effects, among which mobility dependence on vertical field, velocity saturation, channel length modulation, charge sharing and drain induced barrier lowering [5], are treated at device level. Thus, the most computationally demanding part of the model is calculated only once and not as many times as the segments of the channel. Each channel segment then inherits effective values of the respective parameters, namely mobility, effective pinch-off voltage etc. Note that this latter assumption requires that the channel is treated as uniform. Any length related parameter is scaled down according to the segment dimensions. As a result, while keeping the number of the internal nodes unchanged, with respect to the full channel segmentation, the complexity of the NQS model is drastically reduced. As it will be shown in the following section, this simplification does not affect the accuracy of the model.

4

Trading-off accuracy and simulation speed

In Figure 2 simulation results, using the minimal channel segmentation technique, with various choices of the number of segments, are shown. The sim6

ulated circuit consists of a single, long channel nMOSFET, connected in a common source configuration. The gate to source and drain to source ports are considered as input and output, respectively. The Y-parameters of the MOSFET long-channel devices at higher frequencies are importantly affected by the NQS effect. Note, for this analysis, in order to study the NQS effect alone, all extrinsic elements of the EKV3 model, such as overlap capacitances, external resistances and junction diodes, have been disabled. All the following simulations, though, use the full version of the EKV3 model. The differences between the QS single-segment and the 2-, 3- and 5-segment models are substantial. As the number of the segments increases beyond five, the behaviour of the model tends to converge, and the benefit of adding more segments becomes less important. To assess this also quantitatively, another numerical comparison will be performed. The transition from the QS to the NQS behaviour is gradual. The critical frequency which characterizes the NQS regime is given by [2],

fcrit =

1 µUT 15 (qs + qd + 1)3 2π L2 2 qs2 + qd2 + 3qs qd + 52 qs + 52 qd +

5 4

(5)

Substantial NQS effects set in when the frequency reaches one tenth, or a few tenths, of fcrit , and an NQS model is required beyond. Note that fcrit accounts not only for the dependence of NQS effects on channel length and mobility (via the term

µUT L2

), but also, importantly, for bias-dependence covering weak

to strong inversion (the charge terms which follow). For this reason, the present analysis is of general validity, for long-channel MOSFETs, of either channel type, temperature, and any level of inversion, excluding however velocity7

saturation related effects.

In Figure 3, the magnitude and phase of Y-parameters, from the previous analysis, are presented for various segment cases (1, 2, 3, 5, 10, 50) versus the normalized frequency (Θ =

f ). fcrit

Taking as reference the N =50 case, the error

in magnitude of the Y-parameters of the QS model starts to increase when the frequency approaches and exceeds fcrit . The phase of the Y-parameters is even more sensitive to NQS effects. Even at one tenth of fcrit , a certain deviation in phase shift starts to be observed for the QS case. The deviation from the NQS model is summarized in Table 1. Indicatively, the 5-segment model presents an error in Y21 of 2 percent in magnitude and of -1 degree in phase, at a frequency corresponding to fcrit , while for Y11 the corresponding errors are 0.2 percent and 2 degrees.

Figure 4 presents a comparison of the simulation time with the minimal channel segmentation technique, varying the number of segments. The first case, with just two segments, one additional node, is used as a reference and all results are normalized to this case to make the comparison easier. The results confirm the expected increasing complexity of the model as the number of the segments increases.

A comparison of simulation time, between the full and the minimal channel segmentation techniques, is presented in Table 2. Simulation time represents the EKV3 model run as a Verilog-AMS module in a commercial circuit simulator. For the case of 5 segments, the full channel segmentation NQS approach, without any further enhancements, would roughly result in a 3.7 times higher simulation time, compared to a single-channel QS model. Conversely, the minimum channel segmentation NQS model improves this drastically to about 1.9. 8

The direct comparison between the full and the minimal channel segmentation techniques shows the latter to be approximately twice as fast. This result is indicative since it is extracted from a specific circuit and simulation setup and for a specific circuit simulator. It may be expected that results might vary somewhat according to the exact circuit, setup and circuit simulator one uses in order to make comparisons. Considering all the above, the choice of five segments appears to be a favorable compromise between accuracy and computational cost, and may cover the needs for NQS simulation up at least up to fcrit . However, a designer, according to the requirements, may prefer to use more segments, say 10, to achieve improved accuracy or if the simulation frequency lays well above fcrit , say 3 · fcrit . It has to be noted, though, that particularly at high frequencies also the extrinsic elements affect importantly the response of the MOSFET. On the other hand, if a fast response of the simulator is favored or if the simulation frequency does not fall deep within the NQS regime, a choice of 3 segments might prove to be most adequate. Within a Verilog-AMS based modelling approach, it is easy to vary the number of segments and internal nodes. This may be less easy in standard C-code based implementations. The latter will be needed to further assess simulation speed issues.

5

NQS model validation

A channel-segmented transistor should have the same static behaviour as a single-channel transistor, to ensure consistency among QS and NQS models. This is required, for instance, for parameter extraction from DC data: the QS model parameters can then be used, without further adaptation, for the NQS 9

model. One of the most sensitive static aspects in terms of consistency among QS and NQS models is the output conductance, as shown in Figure 5. In Figure 6 the low frequency capacitance of a short channel NMOS device is shown to be consistently modeled by both the QS and minimal channel segmentation NQS versions of the EKV3 model. Note that for these and the following simulations the 5-segment model was chosen. A test for NQS models, based on the linear transmission line theory, has recently been described in [4]. According to this test, a long-channel device, biased at VDS = 0V and in strong inversion, should show an input resistance Rin equal to

1 , 12gds

−1 where Rin is Re(YGG ) and gds is Re(YDD ). In Figure 7, the

consistent behaviour of the EKV3 NQS model with the theory is illustrated. In order to validate the EKV3 NQS model, a comparison to high frequency measurements from a MOSFET device of a modern deep-submicron CMOS technology will be provided. The measurements correspond to the Y-parameters of a single nMOSFET, connected in a common source configuration. The gate to source and drain to source ports are considered as input and output. The results in Figure 8 indicate that the minimal channel segmentation approach covers the NQS behaviour well up to 10GHz, considering five segments. The QS model results are also provided for reference.

6

Conclusions

Channel segmentation is a viable approach to extend a quasi-static (QS) model into the non-quasi-static (NQS) regime, ensuring consistency among small10

signal and transient analysis. To alleviate the increased simulation time, due to additional internal nodes, the minimal channel segmentation approach, used in the context of the EKV3 model, has been described, and its performance analyzed. In this approach, the compact MOSFET model is divided hierarchically into a core part that describes the ideal charge behaviour, and the rest, which covers higher-order effects, such as mobility reduction to vertical field. For each segment of the MOS channel, only the core of the charge model is used, while mobility effects and most length-dependent effects are treated once for the whole channel. Consistency among the multi-segmented channel and singlesegment channel is preserved at low frequencies. At high frequencies, the NQS effects are well described up to 10GHz with a limited number of (e.g. five) channel segments. In this case, the minimal channel segmentation roughly divides the simulation time by a factor of two, with respect to a full channel segmentation model. As a result, the minimal channel segmentation adopted in the EKV3 MOSFET model largely alleviates the increased simulation time with respect to using the full channel segmentation.

References

[1] J.-M. Sallese, A.-S. Porret. A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation. Solid State Electronics, Volume 44, No 6, pp. 887-894, June 2000. [2] A.-S. Porret, J.-M. Sallese, C. Enz. A Compact Non-Quasi-Static Extension of a Charge-Based MOS Model. IEEE Trans. on Electron Devices, Vol. 48, No. 8, pp. 1647-1654, Aug. 2001.

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[3] A.J. Scholten, L.F. Tiemeijer, P.W.H de Vreede, D.B.M. Klaassen. A Large Signal Non-Quasi-Static MOS Model for RF Circuit Simulation. IEDM 1999 Tech Digest, pp. 163-166. [4] H. Wang, X. Li, W. Wu, G. Gildenblat, R. van Langevelde, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen. A Unified Nonquasi-Static MOSFET Model for Large Signal and Small-Signal Simulation. IEEE Trans. on Electron Devices, Vol. 53, No. 9, pp. 2035-2043, Sept. 2006. [5] M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, C. Enz. EKV3.0: An Advanced Charge Based MOS Transistor Model. Chapter in: W. Grabinski, B. Nauwelaers, D. Schreurs (Editors). Transistor Level Modeling for Analog/RF IC Design, ISBN 1-4020-4555-7, Springer, 2006, pp. 67-95. [6] C. Enz, F. Krummenacher, E. Vittoz. An analytical MOS transistor model valid in all regions of Operation and dedicated to low-voltage and low-current applications. Journal on Analog Integrated Circuits and Signal Processsing, Kluwer Academic Publishers, pp. 83-114, July 1995. [7] C. C. Enz, E. A. Vittoz. Charge-based MOS Transistor Modeling. John Wiley & Sons, ISBN 0-470-85541-X, 2006. [8] M. Bucher, A. Bazigos, E. Kitonaki, F. Krummenacher. Recent Advances in the EKV3 MOS Transistor Model. NANOTECH 2006, Workshop on Compact Models, Boston, Massachusetts, May 8-11, 2006. Available online: http://www.nsti.org/Nanotech2006/WCM2006/WCM2006-MBucher.pdf

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Fig. 1. EKV3 model structure and illustration of the principle of the efficient channel segmentation. Note the same equation set that is used for the core model in all three cases (ideal model, quasi-static and non-quasi-static). The part of the model shown here is limited for simplification.

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Fig. 2. Simulation analysis of the minimal channel segmentation approach with respect to the number of the segments (N ). The real and imaginary parts of the Y parameters of a long channel NMOS device, in a common source configuration (VGS = 0.6V ; VDS = 0.5V ), are shown. [square markers: N =1, cross markers: N =2, dotted line: N =3, solid line: N =5, dashed line: N =10, circle markers: N =50]. The frequency goes up to 60GHz. Note that only the intrinsic part of the model is used for this analysis.

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Fig. 3. Argument and phase of the Y-parameters from simulation results, see Figure 2 for details. [square markers: N =1, cross markers: N =2, dotted line: N =3, solid line: N =5, dashed line: N =10, circle markers: N =50]. The Y-axis is the frequency normalized to fcrit ≈ 3GHz. Note that, as in Figure 2, only the intrisic part of the model is used for this analysis.

15

Fig. 4. Simulation time of the minimal channel segmentation for various values of N , normalized to the 2-segment model

16

Fig. 5. Output conductance gds =

dID dVD

of a long channel (L=2um) NMOS device

at different gate voltage VG . Measured data are represented by circles. The QS single-channel EKV3 model (markers: +) and NQS channel-segmented EKV3 model (line) almost coincide with a negligible difference. Y0 = factor of EKV for conductance.

17

ISP EC UT ,

is the normalization

Fig. 6. CGG =

dQG dVG

and CGC =

dQG dVC ,

VC = VS = VD of a short chan-

nel transistor (L=110nm). Measured data are represented by circles (CGG ) and squares (CGC ). The QS single-channel EKV3 model (markers: +) and NQS channel-segmented EKV3 model (line) almost coincide with a negligible difference. C0 =

Q0 UT ,

Q0 = 2nUT COX W L, is the normalization factor of EKV for capaci-

tance. Note the correct modelling of the overlap capacitance in both versions of the model.

18

−1 Fig. 7. The solid line stands for Rin = Re(YGG ), while the dotted line for 1 12gds

=

1 12Re(YDD ) .

The simulation results here are based on the EKV3 NQS model

of an NMOS device, with W/L = 5um/2um at VDS = 0V . For VG higher than the threshold voltage the two lines match, as they should according to the transmission line theory.

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Fig. 8. The real and imaginary parts of the Y parameters of a long channel NMOS device (L=2um), in a common source configuration (VGS = 0.6V ; VDS = 0.5V ). The markers stand for the measurements, the dotted lines for the EKV3 QS model and the solid lines for EKV3 NQS model using the minimal channel segmentation approach (5 segments).

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Table 1 Error results of the NQS model for various numbers of segments and normalized frequencies, taking as reference the model with N =50. For the magnitude, the relative error is shown, e.g.

mag(Yxy (N=1))−mag(Yxy (N=50)) , mag(Yxy (N=50))

while for the phase, the absolute

error is shown, e.g. arg(Yxy (N = 1)) − arg(Yxy (N = 50)). The error gets higher for high frequencies and low number of segments. Θ =

21

f fcrit .

Table 2 Simulation time, normalized to the QS model (N = 5)

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