Materials Science and Engineering B 114–115 (2004) 166–173
Accurate electrical activation characterization of CMOS ultra-shallow profiles T. Claryssea,∗ , F. Dortua , D. Vanhaerena , I. Hoflijka , L. Geenena , T. Janssensa , R. Looa , W. Vandervorsta,b , B.J. Pawlakc , V. Ouzeaudd , C. Defranouxd , V.N. Faifere , M.I. Currente b
a IMEC, Kapeldreef 75, B-3001 Leuven, Belgium KU Leuven, Electrical Engineering Department, INSYS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium c Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium d SOPRA, 26 rue Pierre-Joigneaus, F 92270 Bois-Colombes, France e Frontier Semiconductor Measurements, San Jose, CA, USA
Abstract Understanding dopant diffusion and activation mechanisms is a key issue for future sub-45 nm CMOS technologies. This understanding requires the availability of accurate chemical and electrically active dopant profiles. In this work we will focus on the accurate characterization of the electrical active portion of ultra-shallow junction (USJ) profiles, including a precise sheet resistance determination. Here, we will discuss respectively, sheet resistance measurements with conventional and low weight four point probe (FPP) systems, electrical depth profiling by the spreading resistance probe (SRP), alternative solutions based on probe-spacing experiments with an SRP-tool, and electrical characterization by non-contact, non-destructive optical tools, such as surface voltage based resistance and leakage (RsL) measurements, carrier illumination (CI) and infra-red spectroscopic ellipsometry (IR-SE). The comparison will mainly be based on state-of-the-art, low temperature, 1–2 nm/decade, sub-50 nm depth, chemical vapor deposition (CVD) layers with different thicknesses and dopant levels. Furthermore the activation of boron in solid phase epitaxially regrown (SPER) source-drain structures will be discussed. It will be illustrated that the combination of electrical characterization tools can supply essential information not otherwise obtainable through other means such as secondary ion mass spectrometry (SIMS) chemical profiling. © 2004 Published by Elsevier B.V. Keywords: Electrical activation; CMOS; Ultra-shallow; Sheet resistance
1. Introduction As semiconductor CMOS devices become smaller and more complex as needed for sub-45 nm technology nodes, there is a growing need for characterization tools to determine more accurately the positions and concentrations of the involved dopant species [1]. Especially with respect to the correct sheet resistance determination, one of the most important technology parameters, recently several problems have been encountered related with substrate shorting or material removal due to the penetration of the probes used [2,3]. Given the fast pace in technology progress a timely resolution ∗
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[email protected] (T. Clarysse).
0921-5107/$ – see front matter © 2004 Published by Elsevier B.V. doi:10.1016/j.mseb.2004.07.047
of these issues is mandatory. In this paper, we will focus on the present capabilities in the field of one-dimensional carrier and electrically active dopant profiling in silicon based on the measurement of the sheet resistance and resistivity, the carrier concentration, the electrical junction depth and the mobility. In order to do so, we will use a variety of structures and characterization techniques. The structures involved are low temperature chemical vapour deposited layers [4] with thicknesses varying from 110 nm down to 10 nm and low temperature solid phase epitaxially regrown (SPER) implanted structures (without post-anneal) [1]. The CVD layers are ideal test vehicles due to their near box-like dopant profiles and low defect density. The SPER structures represent a promising future technology choice and as such it is important to assess our electrical characterization capabilities on them.
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With respect to the characterization techniques applied in this work we consider both contact and non-contact techniques. As a base reference for the sheet resistance we use a conventional four point probe (FPP) system operating at 100 g (RS75 OmniMap, probe-type C, denoted 4PP) probe load (probe penetration of more than 100 nm). Subsequently we will consider sheet resistance techniques, which are less and less destructive. We start off with low weight FPP systems using weights as low as approximately 10 g. Next, we consider the variable probe spacing (VPS) technique [5], which operates at 5 g load and is an absolute sheet resistance measurement technique based on the usage of a conventional twoprobe spreading resistance probe (SRP) [6,7] system. Also SRP itself, commonly used for resistivity and carrier depth profiling, i.e. the electrical junction depth determination, will be discussed. Next, we will move to non-contact, i.e. zero weight, techniques. First, we will discuss a new promising resistance and leakage measurement tool, which measures a light-induced surface voltage difference [8]. Next, we will consider the infra-red spectroscopic ellipsometer [9], which is an absolute technique, which besides sheet resistance information also has the capability to directly measure the mobility of the involved layers. Finally, we discuss the carrier illumination (CI) technique [10,11], which is an attractive new tool with a high depth, spatial, and carrier concentration sensitivity.
2. CVD structures As a basis for the envisaged comparison of the above techniques a series of boron doped CVD layers on lowly doped n-type substrates (2 × 1014 atm/cm3 as determined by SRP) have been grown at a temperature of 660◦ C with SiH4 with thickness from 110 nm down to 10 nm as measured at a dopant level of 1019 atm/cm3 . Fig. 1 shows the dopant profiles as measured by secondary ion mass spectrometry (SIMS). Note that the dopant levels in the (nearly) flat portion of the CVD layer vary from 1020 atm/cm3 for the thicker ones to 2 × 1020 atm/cm3 for the thinner ones and that all of them have an interface growth peak of at least 3 × 1020 atm/cm3 . Let us now investigate the electrical activation of these layers. 2.1. Sheet resistance Fig. 2 illustrates that when plotting the conventional FPP data (obtained at 100 g load with more than 100 nm penetration, average values of 49 point mappings, see also Table 1) as the inverse of the sheet resistance (Rsheet ) versus the layer thickness (d) we obtain an almost perfect straight line (correlation coefficient = 0.99939). The error bars shown in Fig. 2 (standard deviation of about 3–4%) are partially due to wafer non-uniformity (SIMS depth variations of up to 2 nm). Although a straight line is in theory expected (1/Rsheet = d/ρ), in practice this may be somewhat of a surprise given the fact that the probe penetration is clearly larger than the involved met-
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Fig. 1. Dopant profiles as measured by SIMS for the sub-100 nm Boron doped CVD structures on n-type 2 × 1014 atm/cm3 substrate.
allurgical junctions (down to 10 nm). In understanding this phenomenon one must keep in mind that, as discussed elsewhere [2], it is the depth and shape of the internal electrical (and not the metallurgical) junction near the probes, which plays a crucial role here. The substrate dopant level mainly determines the electrical junction depth, while its shape depends on the amount of local material removal due to probe penetration. In our case, the substrate is quite lowly doped (internal junction deeper than 600 nm depth), and although undoubtedly the electrical junction is closer to the surface underneath the probes (due to material removal) the substrate shorting is still apparently minimal (straight line in Fig. 2). We will however come back to this point in a moment. From the slope of the linear regression line in Fig. 2 one can deduce a resistivity value of 1.28 × 10−3 ohm cm or a carrier concentration level of 9 × 1019 /cm3 when assuming crystalline mobilities (see further). There is another point to be noted regarding Fig. 2. Namely the fact that the linear regression line through the FPP data does not go through the zero of the graph (as it should), but intersects the x-axes near 5 nm thickness. The latter is considered to be an indication that there is a 5 nm sub layer, which is non-active. The most probable explanation is that this phenomenon relates to the interface layer where the dopant peak is located (see further). Next let us consider what happens when low weight FPP or equivalent techniques are applied down to loads of 5 g. First FPP systems running at respectively 20 g (SSM 240, about 30 nm penetration) and about 10 g (four-dimensions, about 15 nm penetration) have been used. Note that in this context we also consider the VPS technique (5 g, about 5 nm penetration), which is based on the measurement of a series of spreading resistance values on the original surface (no bevel) with five to seven different probe spacings. From the latter the sheet resistance value can be computed as the slope of the linear regression line, through the measured resistance
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4PP (100g) VPS (5 g) SRP (5 g)
9.E-03
9.E-03
8.E-03 7.E-03 6.E-03 5.E-03 4.E-03 3.E-03 2.E-03
8.E-03 7.E-03 6.E-03 5.E-03 4.E-03 3.E-03 2.E-03 1.E-03
1.E-03
0.E+00
0.E+00 0
(a)
4PP (100g) IRSE (0 g) RsL (0 g)
1.E-02
1/sheet resistance (1/ohm)
1/sheet resistance (1/ohm)
1.E-02
20
40
60
80
100
0
120
20
(b) ~ 5nm offset
~ 5nm offset Depth@1e19 (nm)
40
60
80
100
120
Depth@1e19 (nm)
Fig. 2. Inverse of the sheet resistance vs. CVD dopant layer thickness taken at a SIMS level of 1019 atm/cm3 as measured by the investigated sheet resistance techniques. Table 1 Sheet resistances (ohm/sq) as measured by the different tools on the CVD layers discussed in this work. Xj is the SIMS junction depth at 1019 atm/cm3 Wafer
Xj (nm)
FPP (100 g)
FPP (20 g)
FPP (10 g)
VPS (5 g)
IRSE
RsL
SRP profile
D02 D03 D04 D05 D06 D07 D21
11 19 27 37 57 85 114
1931 819 510 376 251 156 117
2079 808 508 373 242 150
2205 846 533 387 251 154
2300 865 543 410 255
2122 950 623 520 351 194 125
3905 1550 765 553 254 166 128
2840 834
values plotted versus the logarithm of their separation, multiplied with π. VPS (sometimes also referred to as SRP-PS) has been shown to be an absolute technique equivalent with FPP data [12]. The present VPS measurements were found to have very little noise, and as such to be very reproducible (within few percent). First consider Fig. 3, where the sheet resistance results are plotted as a function of the applied probe load. For all structures, but especially for the shallower ones, we can observe a systematic trend of a sheet resistance in-
Fig. 3. Sheet resistance vs. probe weight (or non-contact) for different CVD layer thickness.
343 252 142
crease for lower loads. This can be understood, as lower loads will lead to lower penetrations and hence less substrate shorting between the probes as the underlying electrical junction underneath the probes moves deeper (less material removal). This leads to the apparent conclusion that our sheet resistance base reference line (the 100 g data) may still have been affected by a small amount of substrate shorting. A calculation trying to quantify the amount of substrate shorting necessary to bring the VPS value for the shallowest structure (10 nm junction) down to the baseline value (at 100 g) leads to an apparent parallel substrate resistance of about 10,000 ohm, where the actual substrate resistance is much lower, i.e. about 200 ohm. Hence, although the amount of substrate shorting is small it is not zero, and low weight measurements can reveal this. In Fig. 2 also the inverse of the lowest load FPP data (the VPS data) have been plotted versus their layer thickness. It follows, that the resistivity obtained from the slope of the linear regression line (not shown) through the VPS data points is somewhat higher than the baseline value, namely 1.34 × 10−3 ohm cm or 8.5 × 1019 /cm3 assuming crystalline mobility. Again note that the linear regression line through the VPS data (Fig. 2) intersects the x-axes near 5 nm, confirming a non-active (peak) interface layer. In order to further investigate the trend of increasing sheet resistances for lower probe loads, also data with two different non-contact techniques have been collected. The first one,
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referred to as RsL [8], is based on the injection of excess carriers through a modulated, focussed light beam. The generated carriers cause a lateral flow, which gives rise to a lateral surface voltage difference, which is recorded by two sensors near the surface. The ratio of the two measured surface voltages can then be used to extract the underlying sheet resistance (and leakage currents) provided the junction capacitance is known sufficiently accurately. For the latter the knowledge of the substrate doping level is in principle required. The second non-contact technique considered is IRSE, where changes in the polarization of a focussed probe light beam (about 85 m × 200 m in size) impinging on the sample is recorded. From the analysis of the reflection spectra as a function of wavelength (where infra-red light is the most sensitive to dopant variations), one can among others (see further) determine the sheet resistance. The results of both of these non-contact techniques are to be found in Figs. 2 and 3 (and Table 1). From Fig. 3 it can be seen that all of the non-contact methods (RsL and IRSE) reported higher sheet resistance values than the VPS results (except for a match of VPS and RsL results for a thicker (57 nm) layer and the IRSE results for the thinnest (11 nm) layer, where the IRSE errors were reported to be nonnegligible), hence definitely confirming the earlier observed trend of higher sheet resistance values for lower (or zero) loads. Assuming the RsL value is the more accurate sheet resistance value, it follows that a parallel substrate shorting of about 5000 ohm needs to be taken into account to explain the values as measured by the conventional baseline FPP system (100 g) on the shallowest structure. This may be understood by realizing that underneath the probes, where the internal electrical junction bends upwards towards the probes (due to material removal [2]) a small resistive tunnel is created before the substrate can be reached. Hence the shorting effect can be considered to consist out of the substrate resistance in series with two of these tunnels. Based on the simple formula Rtunnel = ρ·L/A, where ρ is the resistivity in the tunnel, L is its length and A is its cross-sectional area, we obtain for the shallowest CVD structure a rough estimate of the resistance of a single tunnel of approximately 2500 ohm (ρ = 20 ohm cm, L = 500 nm, A = πr2 with r = 3.5 m), i.e. about 5200 ohm for the whole shorting circuit (assuming 200 ohm for the substrate). The latter indicates that the assumption of the baseline FPP data being slightly offset by substrate shorting is reasonable and that the noncontact results may well be the more reliable ones. Further work will however, be required to confirm this conclusion. From Fig. 2 it follows that the RsL curve fitting (taking only the sub 50 nm layers into account) gives the highest resistivity for the doped layer, namely 1.43 × 10−3 ohm cm or a carrier concentration level of 8 × 1019 /cm3 . Note that the values from the IRSE have an intermediate value between the VPS and RsL resistivity/concentration values. Both non-contact techniques also confirm the existence of a nonactive interface layer (non-zero intersection point x-axes in Fig. 2).
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2.2. Activation level The different concentration (activation) levels for the sub50 nm layers have been summarized in Fig. 4a. For the thicker (>50 nm) layers all techniques converge towards the conventional FPP concentration level (labelled 4PP). It follows that, still assuming crystalline mobility, we find an apparent activation of about 60% for the thicker layers (about 100 nm) and 35% for the thinner ones (sub-20 nm). The non-contact techniques predict the lowest activation for the shallowest structures. This can be understood by taking into account that the thin layers lie adjacent to the interface peak, which is assumed to be inactive (as will be confirmed further on by other techniques). Consequently it is logical to expect that the first 10–20 nm grown beyond the inactive interface layer are somewhat less active than further on in the growing process (thicker layers). It is noteworthy that there is a discrepancy in activation level for the shallowest structures of up to 30% (Fig. 4a), which is considerably higher than the 3% accuracy targeted by the ITRS roadmap. An important issue relating to the activation degree is whether or not crystalline mobilities can actually be assumed. For this purpose IRSE can be used. Fig. 4b shows the mobilities, which have been measured by IRSE versus the CVD layer thickness taken at a SIMS level of 1019 atm/cm3 . It follows that when we take the average of the measured mobilities and compare this value with the crystalline mobility value, a reduction in mobility of about 30% needs to be taken into account for these CVD layers. Consequently, the carrier concentration levels shown in Fig. 4a need to be increased proportionally, and the correct activation levels are near 90% for the thicker layers and 60% for the thinner ones. 2.3. Electrical junction depth Now let us come back to the apparently inactive interface peak of about 5 nm thickness. If this is the case, then this should be confirmed by other techniques, which are sensitive to the electrical junction depth. These are respectively, conventional SRP, IRSE and CI. Let us start with taking a look at the SRP depth carrier profiles for these CVD layers as shown in Fig. 5a. Although SRP is operating beyond its physical limits when profiling sub-50 nm structures [13], one can still observe two points. First absolute SRP junction depths for different structure thickness follow the SIMS dopant depths as can also been seen from Fig. 5b. Second, despite the limited depth accuracy one finds that on the average the SRP junction depth is somewhat shallower (5–6 nm) than the SIMS metallurgical junction depths (taking into account an uncertainty on the starting point of a few data points at 2 nm depth resolution, no capping oxide present). Again this is better illustrated in Fig. 5b, by the linear regression line through the SRP junction depths plotted versus their corresponding SIMS depths, confirming a 5 nm inactive interface peak. Note that the bevel surfaces were verified to be suffering of only a minimal amount of bevel rounding in the first 5 nm of the depth
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Fig. 4. (a) Carrier concentration vs. probe load (or non-contact) for crystalline and measured (IRSE) mobilities for the sub-50 nm structures. For the thicker structures (>50 nm) all techniques converge towards the 4PP concentration value. (b) Mobilities vs. CVD layer thickness at a SIMS level of 1e19 atm/cm3 as measured by IRSE.
profiles with an optical profilometer (Wyko). The impact of carrier redistribution (spilling) is expected to be negligible as has been observed in earlier work [2]. Although also the carrier levels from SRP on these sub-50 nm layers have a limited accuracy (worst case 100% error), when plotting the inverse of the corresponding sheet resistance data versus layer thickness in Fig. 2, one can observe that the obtained resistivity from the linear regression analysis is still not too far off, i.e. 1020 /cm3 using crystalline mobility (which is the default setting in SRP software). This is for a large part due to the application of a so-called surface damage correction model as discussed elsewhere [14]. Note that the sheet resistances (Rsheet ) here were calculated from the formula: Rsheet =
1 1/ρ(x)dx
where ρ(x) represents the SRP resistivity depth profile. Fig. 5b, also shows the IRSE layer thicknesses (and error bars) as measured simultaneously with the earlier discussed sheet resistance and mobility data. Again a linear regression line confirms the inactivity of the interface region.
Finally let us consider the CI results. CI is a quite recent technique, which uses a modulated pump laser beam with a few micrometer spot size to locally excite excess carriers of up to levels of 1018 –1019 /cm3 . A second probe laser beam is then used on the same spot, to measure the reflection which occurs within the sample due to enhanced changes in refractive index in the surface doped layer and underlying undoped substrate (due to the presence of the excess carriers). Due to a constructive or destructive interference with the surface reflection, one expects a sinusoidal response curve of the CI-signal versus the junction depth as determined by SIMS at a level of 1019 atm/cm3 . This is illustrated in Fig. 6, where the correlation curves are shown for different series of CVD structures with different thickness and different peak active dopant levels ranging from 5 × 1018 up to 1.5 × 1020 atm/cm3 . When carefully comparing the response curve for the present CVD matrix with earlier work (where no interface peaks were present), it clearly follows that the present response curve lies too far to the right by about 5–6 nm. This again is an independent and strong confirmation of the inactivity of the interface peak, as CI has a very strong depth
Fig. 5. (a) SRP carrier depth profiles (with markers) for some of the CVD dopant profiles (no markers) shown in Fig. 1. The horizontal error bars indicate the depth reproducibility of the SRP profiles. (b) Electrical junction depth of IRSE (at 1e20/cm3 ) and SRP (at 1e15/cm3 ) vs. SIMS dopant depth at 1e19 atm/cm3 . The thick line is the linear regresion through both datasets.
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3. SPER structures
Fig. 6. CI-signal vs. SIMS junction taken at SIMS level of 1e19 atm/cm3 , for CVD layers with different thickness and dopant concentration levels. Labels indicate the electrically active peak carrier levels (peak dopant concentration levels are typically a factor of two higher). The correlation curve from this work (level 1e20/cm3 ) is expected to lie more too the left, confirming an inactive interface peak.
sensitivity of up to 0.1 nm. Note that CI due to its micrometer spot size also has a very high spatial resolution. Furthermore, by taking a closer look at the height dependence of the CI response curves which is directly related with the peak carrier level of the involved CVD layers (at a fixed junction depth) one can also deduce a very high carrier level sensitivity of a few percent, given the fact that signals as small as 100 V can be measured reproducibly. The analysis of these CVD layers can hence be concluded by stating that the interface peak of about 5 nm thickness is inactive and that taking into account appropriate mobility values activation levels have been reached of 90% for the thicker and 60% for the thinner structures.
SPER is an enabling technology for sub-45 nm technology nodes. As such it is important to characterize all of its properties accurately. Here we try to determine the maximum activation level of Boron in SPER layers. The SPER layers studied were obtained by a Ge pre-amorphization at 75 keV with a dose of 1015 /cm2 leading to an amorphous–crystalline silicon interface located at about 110 nm. This was done to facilitate the electrical activation study by SRP and FPP (deep enough interface). Next a series of Boron implants was made at 20 keV with doses varying from 1014 up to 1016 /cm2 . Finally, the amorphous layer was regrown at a temperature of 700◦ C in order to activate the dopants in the top layer. It is known that after this low temperature annealing defects remain present beyond the original amorphous interface and dopants beyond this interface are not activated. No postanneal was performed on these structures. The sheet resistances measured on these SPER structures are shown in Fig. 7a. Clearly, the sheet resistance saturates at a level of about 50 ohm/sq for doses of 3 × 1015 /cm2 or higher, indicating the maximum activation level has been reached. Fig. 7b shows the corresponding SIMS dopant and SRP carrier profiles. Two important observations can be made. First the carrier concentration level of the SRP profiles saturates at a level of about 2 × 1020 /cm3 starting at a dose of 3 × 1015 /cm2 , in agreement with the FPP data. Note that as SRP uses default crystalline mobilities, the actual activation level may be somewhat higher. Work is in progress to further characterize these structures with IRSE. Second the SRP profiles (for the higher doses, except for one) display a steep descent (few nanometre per decade) near the 110 nm depth, i.e. the depth of the original amorphized layer. This indicates that only the dopants in the regrown layer are fully activated, as expected. In order to verify, whether the one SRP profile (dose of 7 × 1015 /cm2 ) is actually deeper (or a measurement error is involved) additional CI measurements have been performed, as the latter technique in principle has a high sen-
Fig. 7. (a) Sheet resistance vs. implanted Boron dose for 110 nm thick SPER layers regrown at 700 C. (b) SIMS dopant (no markers) and SRP carrier profiles (with markers) for the SPER structures. Peak carrier level is about 2e20/cm3 and the electrical interface is confirmed by SRP to be near the 110 nm amorphous layer depth.
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Fig. 8. (a) CI experimental power curves (with markers) for the SPER structures shown in Fig. 7b vs. their expected theoretical position (no markers) in the absence of defects. (b) Impact of low dose implantations (unannealed), i.e. amount of point defects, on the CI-signal.
sitivity to the electrical junction depth as illustrated before (Fig. 6). The corresponding, so-called power curves, i.e. the measured CI-signal versus the applied pump laser power, are shown in Fig. 8 a. Let us take a closer look at one particular power curve, namely the one for structure D06 (dose 1014 /cm2 ). Given its very low peak carrier level, namely 1019 /cm3 , it is expected from the general CI-response curves as shown in Fig. 6, that the CI-signal at 75% power is near −5000 V. However, the measured value is about −20000 V, i.e. 15000 V lower. This can only be understood if one also takes into account the presence of a small amount of unannealed vacancies beyond the regrowth interface. As Fig. 8b illustrates, and has been discussed elsewhere [10,11], a small amount of vacancies (∼1013 /cm2 ) is sufficient to bring down the CI-signal by about 15000 V, as observed on these SPER measurements. Hence, knowledge of the precise amount of defects is required in order to correct each of the respective power curves for each structure for their presence, and to be able to extract subsequently the actual underlying electrical junction depth. It can be concluded that at least an activation level of 2 × 1020 /cm3 can be achieved for boron in SPER technology and that CI is presently limited in its junction depth localization on such structures by the need to calibrate it for the presence of the remaining defects.
it appears that the non-contact techniques are to be considered the more reliable ones. We remind the reader that the low substrate doping levels (2 × 1014 atm/cm3 ) used in this study reduced the effect of substrate leakage paths due to effects of probe penetration and electrical punch through to minimal levels. The shifts in sheet resistance values, particularly for the heavier loaded four point probes, would be much more significant for substrate doping levels close to the conditions of shallow junctions in well (about 1016 atm/cm3 ) or pocket/halo (about 1019 atm/cm3 ) profiles. In order to determine the exact activation degree, one needs to know the precise mobility of the involved structure. The latter can be obtained simultaneously with other variables, such as layer thickness, by the IRSE technique, which is an absolute measurement tool, i.e. does not need an external calibration reference. In the present work a somewhat limited sensitivity for the shallower structures has however been encountered. Towards the near future, CI is a very promising technique as it has the intrinsic capability to achieve simultaneously a high depth (0.1 nm), spatial (2–3 m) and concentration (∼1018 /cm3 ) resolution. Further algorithms need however to be developed to make these capabilities commonly available and to take into account the sensitivity of this tool to the presence of defects.
References 4. Conclusions As in the past, it is for future technologies crucial to be able to accurately determine the correct sheet resistance, activation degree and electrical junction depth of the involved structures. In this work a wide variety of characterization techniques has been applied to a number of challenging structures in an attempt to clarify the present situation. Regarding sheet resistance measurements it follows that a systematic increase is observed on CVD grown layers for lower (up to zero, i.e. non-contact) probe loads. As this behaviour can be related to a decrease of substrate shorting,
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