A novel method of improving transition delay fault coverage using multiple scan enable signals

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals N. Devtaprasanna1, A. Gunda2, P. Krishnamurthy2, S.M. Reddy1 and I. Pomeranz3 1. Department of ECE, University of Iowa, Iowa City, IA 52242 2. LSI Logic Corp., Milpitas, CA 95035 3. School of ECE, Purdue University, West Lafayette, IN 47907 Abstract We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

1. Introduction Testing of integrated circuits for delay causing defects is becoming increasingly important to ensure satisfactory shipped product quality level (SPQL). For circuits using scan, there are two approaches to test for delay faults: skewed-load [1] and broadside [2] methods. In the skewedload method, the second pattern of a two-pattern test required for testing delay faults is obtained by a one-bit shift of the first pattern. In the broadside method, the second pattern is obtained from the circuit response to the first pattern. It is well known that the skewed-load method provides a higher delay fault coverage as well as ease of test generation compared to the broadside method. However, the skewed-load method requires significant design effort to achieve at-speed switching of the scan enable (SEN) signal. Due to the resulting impact on design time and area overhead the skewed load method is not used in many industrial designs. The broadside method is preferred in such cases due to the simpler design of the scan enable signal distribution. The method proposed in this work is based on the use of multiple SEN signals suggested earlier in [3,4]. In the work reported here groups of flip-flops in the circuit are connected to independent SEN signals. Some of the SEN signals are asserted high to allow some flip-flops to obtain their second pattern values through shifting the first pattern whereas the remaining flip-flops obtain their second pattern values from the circuit response to the first pattern as in the broadside test method. Unlike the skewed-load method, none of the SEN signals switch between the launch and capture phases. In [4] we gave a method to select flip-flops to be driven by independent SEN signals based on the faults that are not detected by standard broadside tests. Thus this method requires running transition fault ATPG prior to grouping of flip-flops connected to independent SEN signals. This may not be suitable for some design flows. In this work we propose a method to group flip-flops based on the structure of the circuit under test. Another difference

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from [4] is that [4] also considered use of special flip-flops while here we only use standard scan flip-flops. Earlier methods to improve delay fault coverage in scan designs include enhanced scan [5-7], methods to improve fault coverage when the skewed load test method is employed [8,9], methods that improve the delay fault coverage under the broadside approach [3,4], a hybrid test method [10] and a recent DFT procedure [11] meant to reduce the design effort to insure appropriate switching of SEN signal during skewed-load test application. The methods of [3,4] also use multiple control signals similar to the one described here. In Section 2 we describe the proposed method for using multiple scan enable signals. In Section 3 we describe a heuristic procedure for grouping flip-flops into multiple groups with the flip-flops in each group driven by an independent SEN signal. The experimental setup and results are given in Section 4. Section 5 concludes the paper.

2. Proposed approach We illustrate through an example how the fault coverage can be improved by using multiple scan enable signals. Consider the part of a sequential circuit shown in Figure 1. Flip-flops 1A, 2A and 3A belong to scan chain A and flip-flops 1B, 2B, and 3B are part of scan chain B. Assume that the flip-flops are connected in the order of their numerical indices in their respective scan chains. Consider the line g slow-to-fall (STF) delay fault. This fault is untestable using the broadside test method since the initialization condition 1B = 2B = 1 implies 3A = 1 during the launch cycle. Thus the fault effect is blocked from being propagated to flip-flop 1A during the capture cycle. Similarly, the line n slow-to-rise (STR) delay fault is broadside untestable since the initialization condition 2A = 3A = 1 implies 1A = 1 during the launch cycle because j = 1 is implied by the initialization vector. This blocks the propagation of the fault effect to flip-flop 3B. However both these faults can be tested using the skewed-load method. For the line g STF fault, the fault can be tested by obtaining the desired launch pattern value for flip-flop 3A (0) from flipflop 2A, which can be initialized to 0 without any conflict to the fault initialization condition. Similarly, the line n STR fault can also be tested using skewed-load since the desired launch pattern value for flip-flop 1A (0) can be obtained from the previous flip-flop in the scan chain without conflicting with the fault initialization condition.

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Now assume that there are two scan enable signals SEN1 and SEN2. Assume that SEN1 is connected to flipflops 1A, 2A, 1B and 2B and SEN2 is connected to flip-flops 3A and 3B as shown in Figure 2(a). SIN_A and SIN_B are the scan-in inputs. Figure 2(c) shows the contents of the flipflops in the two scan chains during initialization (IC), launch (LC) and capture (CC) cycles required to test the line g STF fault. Initialization vector (1A, 2A, 3A, 1B, 2B, 3B) = (X, 0, X, 1, 1, X) (X = don’t care) is scanned in with both the scan enables SEN1 and SEN2 set to 1. Both flip-flops 1B and 2B are initialized to 1 to set line g to 1. Then the scan enable signal SEN1 is switched to 0 before the launch and capture clocks are applied while SEN2 is held at 1 throughout this test. Assume that the primary inputs Y and Z (referring to Figure 1) are both set to 0 during launch and capture cycles. During the launch cycle flip-flops 1B and 2B are set to 0 through their data inputs driven by Y and Z, and a 1ĺ 0

(referring to Figure 1), which is a don’t care. When the capture clock is applied, it again receives its value from flipflop 2B instead of capturing the circuit response. Thus the proposed approach can be seen as a combination of skewedload and broadside methods with an important difference of some flip-flops not capturing test responses. It should be noted that one can use more than two scan enable signals to achieve additional fault coverage. Various combinations of setting different scan enable signal values can be expected to lead to detection of additional faults. Since the flip-flops connected to a scan enable signal that is asserted high during test cannot capture test responses, the fault coverage achievable with this method is expected to strongly depend on the grouping of flip-flops into subsets driven by the same scan enable signal.

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Figure 1. An example circuit with broadside untestable faults transition is launched at the target fault site. If a slow-to-fall delay fault is present, then the value of line g will be 1 through the launch and capture cycles otherwise it will be 0 for the fault-free circuit when the capture clock is pulsed. Since SEN2 = 1, flip-flop 3A receives its launch cycle value (0) from flip-flop 2A instead of through its functional data input. Therefore the fault effect can be propagated to flipflop 1A and it is captured during the capture cycle since the scan enable SEN1 of flip-flop 1A is 0. Similarly line n STR fault can be tested if SEN1 = 0 and SEN2 = 1 during the launch and capture cycles and additionally SIN_A is set to 0 during scan in of the initialization vector. Thus both broadside untestable faults can be tested using the proposed method using two independent scan enable signals. It is important to note that during the tests described above the scan enable signals are held constant at 1 or 0 during the launch and capture cycles and hence they need not have the ability to switch at-speed. Another important point to note is that the flip-flops connected to the scan enable signals that are held at 1 perform a shift operation during the launch and capture cycles and hence they do not capture test responses. For example consider flip-flop 3B. This flip-flop is connected to SEN2, which is held at 1 through the test shown in Figure 2(c). When the launch clock is applied, the output of flip-flop 2B which is 1 is latched into 3B instead of the functional input from line p

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Figure 2. (a) Scan enable connections (b) Timing waveform of SEN1 and SEN2 signals (c) Flip-flop contents during test for line g slow-to-fall delay fault

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3. Grouping of flip-flops In this section we describe a heuristic method for partitioning the flip-flops into groups with each group connected to a different SEN signal. Let the set of flip-flops connected to the same SEN signal be called a scan enable group (SEG). The proposed heuristic is motivated by the following observation. A broadside untestable fault is called potentially testable if it can be activated and propagated to a flip-flop i by asserting one or more SEN signals during test. However if flip-flop i is also connected to a SEN signal that is required to be asserted high, then the potentially testable fault remains untestable because the fault effect cannot be captured by the flip-flop. If there are no functional dependencies between the flip-flops in the same SEG, then all potentially testable faults can be tested. Definition 1: A dependency graph of a sequential circuit is an undirected graph G = {V, E}, where each flipflop i in the circuit is represented by a vertex vi in G and an edge (vi, vj) between vertices vi and vj, vi  vj, is present iff there is a path from flip-flop i to flip-flop j or vice versa through the combinational logic of the sequential circuit. Note that dependency of a flip-flop i on itself is not represented in the graph, i.e., there are no self-loops. Definition 2: A set of vertices V″ ⊆ V of an undirected graph G = {V, E} is called independent if there does not exist an edge between any pair of nodes in V″. Definition 3: A maximal independent set (MIS) of an undirected graph G = {V, E} is an independent set of vertices V′ such that addition of any vertex vk ∈ V − V′ to V′ will result in a set of vertices that is not an independent set of vertices. If a SEG is an independent set then clearly any fault which is activated and propagated by state transitions in some flip-flops in the SEG will not propagate to a flip-flop in the same SEG. In our approach we chose maximal independent subsets as SEGs to allow maximum utilization of independent SEN signals to activate and propagate fault effects. For this reason if N SEN signals are used we select (N-1) maximal independent subsets of the dependency graph G to form all but one SEGs, with the flip-flops not included in any selected independent set forming the last SEG. We do this by iteratively picking independent subsets of G as described below. 1. 2. 3. 4. 5.

Procedure ObtainSEGs(G1, N) Let G = G1 (V = V1, E = E1) For i = 1 to N-1 SEGi = ObtainMIS(G) G = Subgraph of G1 for the set of vertices {V − SEGi} 6. Endfor 7. SEGN = V 8. Endprocedure

Figure 3. Procedure for obtaining scan enable groups The procedure for obtaining scan enable groups, called ObtainSEGs(), is shown in Figure 3. Let G1 = {V1, E1} be the dependency graph of a given circuit and let N (≥ 2) be

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the number of desired scan enable groups denoted by SEG1, …, SEGN. The procedure begins by copying the input graph G1 to G. The first (N-1) SEGs are obtained by executing the loop from line 3 to line 6 (N-1) times. During each pass, a maximal independent set of the graph G is obtained by procedure ObtainMIS(). This MIS is assigned to SEGi in the ith iteration. Then the graph G is updated by removing all the vertices that are in SEGi. The vertex set of graph G at the end of the (N-1)th iteration is assigned to SEGN. Procedure ObtainMIS() in line 4 returns a maximal independent set of an undirected graph that does not contain self-loops. In our experiments, this procedure is implemented using the neural network based algorithm given in [12]. It should be noted that the method of [12] does not guarantee returning the largest maximal independent set of a graph.

4. Experimental results We implemented the proposed method on full scan versions of the larger ISCAS-89 circuits as well as two industrial designs. Deterministic test generation was performed with a commercial ATPG tool with the constraints that primary inputs do not change between launch and capture cycles and primary outputs are not observed for fault effects. These constraints are commonly used in the industry for compatibility with testers that cannot reliably change inputs at-speed as well as strobe the outputs at-speed. Test generation was performed with an abort limit of 100 (150 for industrial circuits) and the results are reported for the set of uncollapsed faults. In Table 1 we give the results of our experiments for the ISCAS-89 benchmark circuits. For each circuit up to five SEN signals are used. The scan enable groups were obtained by applying the procedure ObtainSEGs() described in Section 3. In this table, the transition delay fault coverage, test pattern count and ATPG run time are given for broadside test sets and for the case when the circuit has two, three, four and five scan enable signals (groups). The last row of the table gives the average value of each column for all the circuits. It can be seen that with only two SEN signals, an average fault coverage improvement of 4.51% is achieved along with ATPG runtime reduction of 42%. When five SEN signals are used, the fault coverage is improved by an average of 7.0% along with runtime reduction of 66%. However as the number of SEN signals is increased the number of test patterns increases as more faults are detected. In Table 2 we compare the proposed method with the hybrid method of [10]. We give the percentage improvement in fault coverage for the hybrid method (column 2) as well as using our method with two (column 3), three (column 4), four (column 5) and five (column 6) SEN signals, respectively. It can be seen that a substantially higher improvement in fault coverage is obtained for circuits s9234, s15850, s38417 and s38584. Two exceptions are s13207 and s35932. While the improvement in fault coverage is comparable for s13207, for s35932 the proposed method improved the fault coverage by only 1.51% compared to the 5.78% improvement obtained with the hybrid method. In Table 3, we give the characteristics of the two industrial designs used in our experiments. In Table 4,

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[2] J. Savir and S. Patil, “On Broad-Side Delay Test”, Proc. VTS, 1994, pp. 284-290. [3] I. Pomeranz and S. M. Reddy, “On Achieving Complete Coverage of Delay Faults in Full Scan Circuits Using Locally Available Lines”, Proc. ITC, 1999, pp. 923-931 [4] N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. M. Reddy and I. Pomeranz, “Methods for Improving Transition Delay Fault Coverage Using Broadside Tests”, Proc. ITC, 2005 [5] B. I. Dervisoglu and G. E. Stong, “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement”, Proc. ITC, 1991, pp.365-374. [6] J. P. Hurst and N. Kanopoulos, “Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits”, Proc. ATS, 1995, pp.346-352. [7] C. T. Glover and M. R. Mercer, “A Method of Delay Fault Test Generation”, Proc. DAC, 1988, pp. 90-95. [8] W. Mao and M. D. Ciletti, “Reducing Correlation to Improve Coverage of Delay Faults in Scan-Path Design”, IEEE TCAD, 1994, pp.638-646. [9] J. Savir and S. Patil, “Scan-Based Transition Test”, IEEE TCAD, 1993, pp.1232-1241. [10] S. Wang, X. Liu and S. T. Chakradhar, “Hybrid Delay Scan: A Low Hardware Overhead Scan-based Delay Test Technique for High Fault Coverage and Compact Test Sets”, Proc. DATE, 2004, pp. 1296-1301. [11] N. Ahmed, C. P. Ravikumar, M. Tehranipoor and J. Plusquellic, “At-Speed Transition Fault Testing With Low Speed Scan Enable”, Proc. VTS, 2005. [12] Y. Shrivastava, S. Dasgupta and S. M. Reddy, “Neural Network Solutions to a Graph Theoretic Problem”, Proc. IEEE Intl. Sym. on Circuits and Systems, 1990, pp. 2528-2531.

results of experiments on the industrial designs are presented similar to Table 1. For Ckt1, 2.94% improvement in fault coverage is achieved with the use of two SEN signals. For five SEN signals, the fault coverage is 89.99%, which is comparable to the skewed-load coverage of 90.35% for this circuit. For Ckt2, the fault coverage increases to 86.18% with two SEN signals compared to the broadside fault coverage of 85.03%. When four or five SEN signals are used, the fault coverage for the proposed method is higher than that by the skewed-load method for this circuit. Using five SEN signals the proposed method achieves a transition fault coverage for these two circuits that is within less than 1% of the fault coverage achievable by enhanced scan.

5. Conclusions We presented a method to partition the scan cells of a circuit under test into groups and connect the scan cells in each group to an independent SEN signal. We demonstrated that circuits designed using the proposed method have higher transition delay fault coverage. The proposed heuristic procedure for grouping the scan cells is based on identifying maximal independent sets of nodes in a graph representing the circuit under test. Experimental results on benchmark circuits and industrial circuits were given to illustrate the effectiveness of the proposed procedure.

References [1] S. Patil and J. Savir, “Skewed-Load Transition Test: Part I, Calculus”, Proc. ITC, 1992, pp. 705-713.

Table 1: Experimental results for ISCAS-89 benchmark circuits Ckt. name S9234 S13207 S15850 S35932 S38417 S38584 Avg.

1 SEG (broadside) TDF # of run cov. patt. time 75.38 469 166 72.39 403 534 63.86 261 1418 69.77 69 104 96.11 382 177 63.73 563 1136 73.54 358 589

TDF cov. 80.14 78.45 74.59 70.79 96.46 67.87 78.05

2 SEGs # of patt. 478 452 405 95 468 910 468

run time 139 530 445 92 197 652 343

TDF cov. 81.06 80.80 76.28 71.16 96.55 69.49 79.22

3 SEGs # of patt. 491 540 412 119 497 809 478

run time 121 394 340 79 188 515 273

TDF cov. 81.57 83.45 77.19 71.28 96.59 70.43 80.08

4 SEGs # of patt. 503 607 435 128 519 863 509

run time 110 162 296 77 188 451 214

TDF cov. 82.12 83.97 78.09 71.28 96.66 71.12 80.54

5 SEGs # of patt. 528 624 457 122 548 864 524

run time 100 149 278 77 181 404 198

5 SEGs # of patt. 5621 12709

run time 1441 4985

Table 2: Comparison with the hybrid method of [10] Hybrid method [10] 1.97 11.78 6.39 5.78 0.04 2.99

Ckt. name S9234 S13207 S15850 S35932 S38417 S38584

2 SEGs

3 SEGs

4 SEGs

5 SEGs

4.76 6.06 10.73 1.02 0.35 4.14

5.68 8.41 12.42 1.39 0.44 5.76

6.19 11.06 13.33 1.51 0.48 6.70

6.74 11.58 14.23 1.51 0.55 7.39

Table 3: Profiles of industrial circuits Ckt1 Ckt2

Num. of gates 346448 446102

Num. of FFs 27659 35076

Num. of TDF faults 1114032 1340900

Broadside TDF cov. 85.25 85.03

Skewed-load TDF cov. 90.35 86.71

Enhanced Scan TDF cov. 90.91 87.85

Table 4: Experimental results for industrial circuits Ckt. name Ckt1 Ckt2

1 SEG (broadside) TDF # of run cov. patt. time 85.25 3502 1597 85.03 8839 4266

TDF cov. 88.19 86.18

2 SEGs # of patt. 4235 10656

run time 2064 5491

TDF cov. 89.09 86.63

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3 SEGs # of patt. 4736 11446

run time 1737 4934

TDF cov. 89.63 86.86

4 SEGs # of patt. 5122 12036

run time 1406 4823

TDF cov. 89.99 87.07

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