A Low Power, High SFDR, ROM-Less Direct Digital Frequency Synthesizer

A Low Power, High SFDR, ROM-Less Direct Digital Frequency Synthesizer H.Jafari

[email protected]

A.Ayatollahi

S.Mirzakuchaki [email protected]

[email protected]. ir

E. E. Dept., Iran Univ. of Science & Tech.(IUST), Narmak, Tehran, IRAN Abstract - This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is -91.5ldBc. A DDFS IC has been designed in HP 0.5tm standard N-Well CMOS process technology, and that's layout has 2.489mm2 area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz. Index Terms- Direct digital frequency synthesizer (DDFS), frequency synthesizer, ROM-Less.

I. INTRODUCTION Direct digital frequency synthesizers (DDFS) are now playing an increasingly role in modem digital communication systems because of their characteristics of fast frequency switching and excellent frequency and phase resolution [1]. Almost all DDFSs are designed by using an architecture developed by Tiemey, Rader and Gold [2], as shown in Fig. 1. The phase argument to the sine-computation block is generated by exploiting the modulo 2N overflow of an N-bit accumulator, which can be adjusted by a frequency control word (W). The sine-computation block converts the phase values into a digital representation of a sine wave. The digital sine wave can be converted into its analog counterpart by a digital-to-analog converter and a low-pass filter. The 2N binary words of the accumulator are mapped into phase values such that:

m=n-

27r

.2N(N)

Where m is the binary word of the accumulator, and p is the phase value between 0 and 2m. The output frequency of the DDFS can thus be expressed as:

0-7803-9339-2/05/$20.00 02005 IEEE.

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f

W2fclk 2N

W