A low-cost 90nm RF-CMOS platform for record RF circuit performance

4B-4 A low-cost 90nm RF-CMOS platform for record RF circuit performance W. Jeamsaksiri, D. Linten1, S. Thijs, G. Carchon, J. Ramos, A. Mercha, X. Sun, P. Soussan, M. Dehan, T. Chiarella, R. Venegas, V. Subramanian3, A. Scholten5, P. Wambacq2, R. Velghe6, G. Mannaert, N. Heylen, R. Verbeeck, W. Boullart, I. Heyvaert, M. I. Natarajan, G. Groeseneken4, I. Debusschere, S. Biesemans and S. Decoutere IMEC, Kapeldreef 75, Leuven, Belgium 3001, 1 is also a PhD student at 2VUB, Dept. ELEC-ETRO, 3 is also a PhD student at 4KU Leuven, ESAT-Department, Leuven, B-3001 Belgium, 5 Philips Research Labs, Eindhoven, Netherlands, 6Philips Research Leuven, Belgium.

Abstract

A 90nm CMOS technology has been used as the baseline for a low-cost RF-CMOS platform, with improved analog/RF performances of the active and passive devices. The 65 nm gate length NMOS exhibits 240GHz peak fmax and 170GHz peak fT. A peak Q of 40@5GHz is measured for a symmetrical 2.7 nH Above-IC inductor. This combination leads to a world record performance of a monolithic 5 GHz RF CMOS low noise amplifier presenting a very high gain of 18dB and very low noise figure of 1.5dB, for only 4.8mW power consumption.

Introduction

The potential of 90nm RF-CMOS technology is accepted as attractive for RF applications well into the GHz range [1,2]. Concerns remain with respect to cost and power-performance trade-offs mainly imposed by passive component limitations. Therefore the real challenge has moved to integrated passive components, which are the key technological differentiators that limit the signal degradation and power consumption. The paper demonstrates that careful process tuning and layout optimisation [3] improves the NMOS performance, demonstrated by the intrinsic gain (gm/gds), the cut-off frequency fT, and the maximum oscillation frequency fmax. Next the performance of the MIM capacitor and varactor will be described. In contrast to classic realizations of spiral inductors, using multiple levels of top-metal layers, low-cost high-Q Above-IC inductors realized in 5µm thick Cu, benefit from the extremely low series resistance and capacitive coupling to the substrate. These inductors outperform the classic realizations, resulting in major reduction of noise figure and improvement of the power-gain trade-off of RF circuits. Finally, the potential of this RF-CMOS platform is demonstrated with a monolithic integrated 5 GHz RF CMOS LNA with highest ever-reported performance.

Technology and Layout

The 90nm CMOS process [1] used as the baseline process for this RF-CMOS platform is fabricated on 20 Ohm.cm substrates and has 65nm physical gate length and DPN gate oxide of 1.5 nm. The Above-IC layers have been realized on top of this CMOS process with 3 to 5 levels of metal, Cu/oxide back-end. The 5µm thick electroplated Cu layer is separated from the passivation by a 16µm BCB (benzo-cyclobutene, K=2.65) layer, an 8µm top BCB layer prevents the Cu-layer from oxidation, overpasses are realized on a top Cu/Ni/Au layer which acts as UBM for solder bumps in case flip-chip is used [2]. The thick Above-IC dielectrics lower the parasitic capacitance to the patterned ground shields hereby increasing the inductor resonance frequency while the thick Cu yields low series resistance. The low complexity planar MIM capacitors module uses TaN electrodes and a dielectric stack of 9 nm oxide/30 nm nitride/9 nm oxide (ONO) optimized for a 1.1 fF/µm2 specific capacitance and to ensure high voltage linearity and low leakage.

Digital/Analog performances

Fig. 1 shows the ring oscillator delay as a function of the total drive current measured at different supply voltages of 1.1, 1.2, and 1.3 V. At 1.2 V, the minimum delay is 12 ps. with total drive current of 1100 µA/µm. The gm/Id ratios of the nominal transistor measured for all Vd biases reach the maximal value of 38 V-1 in the weak inversion regime (see Fig. 2). At Vd=1.2 V and Vg-Vth =100 mV, the gm/gds ratio as high as 23 is achieved, well above ITRS specification [4]. Fig. 3 shows also the expected decrease in gm/Id ratio in the weak inversion regime when the temperature

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increases from 298 K to 398 K with negligible performance degradation in the strong inversion.

RF performance of NMOS device: f T and fmax

The transistor (3µm finger width*64 fingers*65nm Lg) is optimized towards high fmax, and high fT [3]. fT and fmax are extrapolated, at 40GHz, using -20dB/dec slope, from current gain |h21|2 and Mason’s gain |U|, respectively. The extrapolated fT and fmax as functions of the drain current with fixed Vds=0.4, 0.6, 0.8, 1, and 1.2 V, are illustrated in Fig. 4. The peak fT and fmax of 170GHz and 240GHz are extrapolated at Vd=1.2V and Vg at 0.8 V and 0.7 V, respectively. At 50 GHz fT, the current consumed is only 15 µA/µm, well within ITRS specifications [3]. The NFmin measured at 2 GHz, Vd=1.2V and sweeping Vg from 0.3 - 0.8 V gives an average NF50 from moderate to strong inversion (Vg>0.35 V) of 0.5dB (Fig. 5), fulfilling ITRS requirement [4].

RF Passive components

The MIM capacitor ONO dielectric balances the negative and positive quadratic voltage linearity coefficients of the oxide and nitride layers, resulting in Vcq=-5.7 ppm/V2 (Fig. 6). Fig. 7 shows the Q-factor at 5 GHz versus the capacitance value. At 5 GHz, the 3 pF capacitor has a Q-factor over 100. This improvement over previously reported values [1] is obtained by shunting the TaN bottom plate with the underlying Cu metal layer. The accumulation MOS-Varactors with 1.5 nm DPN oxide exhibit a tuning capacitance range (CTUNE) of 6 (Fig. 8). The center of tuning range is well placed at 0 V. The Above-IC inductors are optimized to obtain the highest Q factor at the operating frequency. Single ended Q-factors above 40 have been measured for above-IC inductors as shown in Fig. 9.

Circuit - Record performance of 5 GHz LNA

The great potential of this 90nm bulk RF CMOS platform is demonstrated with a monolithic 5 GHz common-source cascode LNA with inductive source degeneration (fig. 10). The LNA is matched to 50 Ω at both input and output, while drawing 4 mA from a 1.2 Volt supply. At 5 GHz this LNA has a gain of 18dB, noise figure of 1.5 dB, input and output matching of -16 dB and -38 dB, respectively (see Fig. 11). A similar LNA processed with the same FEOL, but with a 5LM BEOL, resulted in a power gain of 13.5 dB, noise figure of 2.2dB, drawing 7.5mA, which clearly indicates the improvement achieved by the use of high-Q Above-IC inductors. To the authors’ knowledge, this design is the first monolithic 5 GHz RF CMOS LNA, which presents such record performances.

Conclusions

A 90 nm CMOS technology with high fT (170GHz), fmax (240GHz) and a portfolio of high Q passive components in back end and in Above-IC have been successfully integrated in a versatile platform leading to a record performance monolithic 5 GHz RF CMOS LNA.

References [1] W. Jeamsaksiri et al, VLSI2004, 10.3 pp. 100-101. [2] G. Carchon et al. paper 21.5, ISSCC2005 [3] L.F.Tiemeijer et al, IEDM 2001, 10.4.1-10.4.4 and IEDM 2004 [4] ITRS Roadmap http://public.itrs.net Acknowledgements The authors would like to thank IMEC Pilot line for silicon processing and European Commission for supporting the IMPACT IST-2000-30016 project and the Flemish IWT for their financial support.

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Fig 10: Microphotograph and schematic of the monolithic 5 GHz LNA with inductive source degeneration. The supply voltage is VDD=1.2V for 4mA current transistor M1A, Transistor M1A M2 are respectively 110µm wide with 54 fingers, and 60µm wide with 20 fingers. Lg, Lload and Ls are above IC inductors of 4nH, 2.7 nH and 0.7 nH with a single ended Q factor of 30,40 and 28 respectively.

Fig. 11: Input and output impedance of the 5GHz LNA: S11 = - 18 dB, and S22 = -38 dB and NF50 is ~1.5dB at 5GHz.

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