IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 2, FEBRUARY 2011
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A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier Rahul Singh, Yves Audet, Member, IEEE, Yves Gagnon, Yvon Savaria, Fellow, IEEE, Étienne Boulais, and Michel Meunier
Abstract—This brief presents a rail-to-rail input–output precision operational amplifier with integrated laser-trimmable polysilicon resistors for reducing the input offset voltage. The amplifier is fabricated in a standard Taiwan Semiconductor Manufacturing Company 0.18-µm complementary-metal–oxide–semiconductor process technology. The resistors’ trimming sequence allows for minimizing the offset voltage over the complete input common mode voltage range (ICMR) extending from the ground to the supply. Experimental results are presented to demonstrate the steps involved in offset-voltage trimming. The prototype amplifier drives a 400-pF capacitive load and operates from a 3.3-V supply. The amplifier is unity-gain stable with a phase margin of 58◦ and has an open-loop direct-current gain greater than 130 dB with a unity-gain bandwidth of 0.5 MHz. Experimental results show that an untrimmed input offset voltage ranging from +0.1 to +0.5 mV over the ICMR was reduced to −30 to + 30 µV. Index Terms—Complementary-metal–oxide–semiconductor (CMOS) analog integrated circuit (IC), input-offset-voltage trimming, precision operational amplifier, rail-to-rail differential amplifier.
I. I NTRODUCTION RECISION-operational-amplifier integrated circuits (ICs) were primarily developed to fulfill the requirement of testing and measuring circuit parameters [1]. Such amplifiers have evolved to find applications in portable equipment, sensor interface, and industrial sector for monitoring and performing high-accuracy measurements. Some of the earlier reported classic precision amplifiers were developed using bipolarjunction-transistor fabrication processes [2], operating at high supply voltages. Complementary-metal–oxide–semiconductor (CMOS) process technologies, providing a lower manufacturing cost and a lower supply voltage, represent a good alternative for analog integrated amplifiers. A precision amplifier is characterized by an input offset voltage lower than 150 µV, an open-loop voltage gain greater than 120 dB, and a minimum common-mode rejection ratio (CMRR) and a power-
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Manuscript received June 15, 2010; revised October 6, 2010; accepted November 26, 2010. Date of current version February 24, 2011. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada and in part by the Canadian Microelectronic Corporation. This paper was recommended by Associate Editor H. Barthelemy. R. Singh is with Advanced Micro Devices, Markham, ON L3T 7X6, Canada. Y. Audet and Y. Savaria are with the Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC H3C 3A7, Canada (e-mail:
[email protected]). Y. Gagnon is with Dolphin Integration, Laval, QC H7T 1S9, Canada. É. Boulais and M. Meunier are with the Department of Engineering Physics, Ecole Polytechnique de Montreal, Montreal, QC H3C 3A7, Canada. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2104011
supply rejection ratio (PSRR) of 85 dB [1]. The input offset voltage is an important parameter that determines the directcurrent (dc) accuracy of a precision amplifier. In the case of rail-to-rail CMOS amplifier, the input stage of a CMOS railto-rail amplifier consists of an n-channel MOS (NMOS) and a p-channel MOS (PMOS) differential pairs operating in tandem to cover the input common mode voltage range (ICMR). Therefore, the offset voltage will vary depending on whether the NMOS, the PMOS, or both differential pairs are operating. In terms of alternating-current (ac) parameters, a nonuniform offset voltage over the ICMR will deteriorate the CMRR [3]. Most commercial precision amplifiers exploit continuous-time IC trimming techniques in addition to an external potentiometer to reduce the offset voltage [4], [5]. Various on-chip trimming techniques exist for precision amplifiers, including Zener zapping [6] for bipolar and bipolar-CMOS (BiCMOS) processes, laser trimming of thin-film resistors [7], and laser cutting [8] available in bipolar, BiCMOS, and CMOS processes. Offset voltages in the order of 10–100 µV are obtained with these techniques. Recently, a single-stage folded cascode amplifier using floating-gate transistors as trimming elements achieved an offset voltage of ±25 µV [9]. The open-loop gain is however limited to 63 dB due to the single-stage topology employed. For these circuits, the offset voltage remains the same over the entire ICMR since it involves a single differential input stage. However, for a precision rail-to-rail amplifier input stage, the offset voltage is trimmed and specified over the complete ICMR [10] due to the dual-input differential pairs comprising of NMOS and PMOS transistors. This brief proposes an architecture of a three-stage rail-torail input/output (I/O) precision amplifier. The objective of this work is to exploit a standard CMOS process to design a precision rail-to-rail I/O amplifier having a low offset voltage over the entire ICMR and a large open-loop gain exceeding 120 dB. This brief unfolds as follows. Section II presents the amplifier topology with a focus on physical-design considerations. Section III describes the laser technique employed for polysilicon resistor trimming. Experimental results on the offset-voltage reduction and important measured dc and ac characteristics are reported in Section IV. A conclusion follows in Section V. II. A MPLIFIER A RCHITECTURE A. Design Considerations A number of design aspects need to be considered while designing a precision CMOS operational amplifier. The basic
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 2, FEBRUARY 2011
Fig. 1. Schematic diagram of the proposed rail-to-rail I/O CMOS precision operational amplifier.
building cells for the amplifier presented in Fig. 1 are differential pairs, current mirrors, and pairs of load resistors. The elements within these cells should be geometrically identical. The device mismatch between these elements is one of the major factors that contribute to the input-referred offset voltage. The device mismatch occurs due to process variations during manufacturing, which contributes to the threshold-voltage VT and current-factor β mismatch [11]. In order to minimize these variations, matched transistors are designed to have a large active area (W • L). The same concept is also applied to the design of matched resistors in the amplifier [12]. Additionally, large active areas combined with low dc bias current minimize the low-frequency 1/f noise. In CMOS-based precision analog design, matching is also a function of biasing points. A differential pair biased by a tail current source is operated at a low gate-overdrive voltage (VGS − VT ) to reduce the gate–source voltage mismatch. On the other hand, a current mirror is biased at a high gate-overdrive voltage to reduce the drain-current mismatch [11]. In other words, differential pairs are operated in the weak-inversion region, and current mirrors are biased toward the strong-inversion region to attain an overall better matching. A precision amplifier requires a high open-loop dc gain in order to have a low dc gain error under a closed-loop operation. Most industry standard precision amplifiers are characterized by an open-loop dc gain in excess of 120 dB [1], [2]. The amplifier architecture presented here is designed to operate over a low supply voltage of 3.3 V. The design tradeoff considered in this work is to maintain a rail-to-rail I/O feature while operating at a low supply voltage. The rail-to-rail precision amplifier consists of three cascaded stages of amplification to achieve a high open-loop dc gain. In the case of cascaded amplifier stages, it is the input stage that has the largest contribution toward the input offset voltage. Hence, the design of the input stage is critical to obtain a low untrimmed offset voltage. Laser-trimmable polyresistors are integrated in the input stage to reduce the offset voltage further. B. Topology Description The schematic of the proposed operational amplifier architecture is shown in Fig. 1. The input or first stage consists
of the NMOS (M1 −M2 ) and PMOS (M3 −M4 ) differential pairs operating in parallel. The differential pairs are connected to a current-summing stage consisting of P+ polysilicon resistor R1 −R8 of equal value and transistors M9 −M12 . The current-summing stage combined with the parallel operation of the differential pairs provides a rail-to-rail input feature with a differential output obtained at the drains of M11 and M12 . Resistors R1 −R2 and R7 −R8 form the upper and lower laser-trimmable resistors for the offset-voltage reduction, respectively. A rail-to-rail differential amplifier requires some form of control circuitry to maintain a constant transconductance Gm over the ICMR. A constant Gm of the input stage allows for a constant dc gain and an optimal frequency compensation over the ICMR. The design of the Gm control circuit depends on the strong- or weak-inversion operation of the input stage. To optimize for matching and noise, the differential pairs M1 −M2 and M3 −M4 operate in the weak inversion [5]. The Gm of a MOS transistor in this region is linearly proportional to the drain current. The Gm control circuit used here is a classic current steering stage made up of a current source M5 , a current steering transistor M6 , and a unit ratio current mirror M7 −M8 . The purpose of this stage is to maintain a constant sum of tail currents to the PMOS and NMOS differential pairs as the input common mode (ICM) voltage changes. The input stage is followed by a second stage, which consists of a simple differential amplifier formed by transistors M13 −M17 . The output terminals from the first stage are obtained at the low-impedance drain node of M11 and the highimpedance drain node of M12 , which are connected to the differential input transistors of the second stage, i.e., M14 and M15 . This topology helps to reject any common-mode signal component due to the first stage. The last or output stage is a common-source class-AB amplifier formed by M23 −M24 to provide a rail-to-rail output voltage swing while driving a large capacitive load. The output of the second stage is connected to the gate of M24 . In between these two stages, there is an intermediate stage with a diode-connected load [13] formed by transistors M18 to M20 . The intermediate stage combined with M21 −M22 drives the gate of the large transistor M23 . The three stages of the amplifier are stabilized for the closed-loop operation by using double pole-zero cancellation techniques for
SINGH et al.: LASER-TRIMMED RAIL-TO-RAIL PRECISION CMOS OPERATIONAL AMPLIFIER
Fig. 2. Resistance lowering in parts per million following a single 532-nm 300-ns laser irradiation on a 4 µm × 40 µm 800-Ω n+ polysilicon-resistor device fabricated in a CMOS 0.18-µm process. The melting threshold is 0.33 J/cm2 . (Inset) Normalized resistance values of the polysilicon-resistor device following several single 532-nm 300-ns 0.32-J/cm2 laser irradiations.
large capacitive loads [14]. The compensation network involves two nulling resistors, i.e., R9 and R10 , along with two Miller capacitors denoted as C1 and C2 . A CMOS proportional-to-absolute-temperature circuit is used to generate bias voltages VB1 and VB2 for the amplifier. The circuit is a variant of the topology described in [15]. III. T RIMMING FOR THE O FFSET VOLTAGE R EDUCTION Polysilicon-resistor films are widely used in standard CMOS processes for their availability and their high value of sheet resistance. A polysilicon resistor trimming technique suitable for standard CMOS processes [16] has been exploited for this work to demonstrate the concept of the offset reduction in railto-rail amplifiers. The laser-trimming apparatus has been built in our laboratory from a neodymium-doped yttrium-aluminumgarnet laser and standard optical components. Unlike thinfilm resistor trimming where the resistance value is increased by laser ablation, here, the laser energy is absorbed by the polysilicon film yielding to a localized crystallization of the material, thus allowing a very precise reduction of the resistivity of the affected zone. The trimming method involves the local heating of the surface of the resistor using a visible 532-nmpulsed tightly focused laser with a fluence below the polysilicon melting threshold of 0.33 J/cm2 . The laser beam goes through the transparent dielectric layers to reach and finely alter the polysilicon thin film. This resistance can thus be adjusted to any lower value by varying the laser fluence, the pulse number, the pulsewidth, and the number of laser intervention on the device. The use of a discrete nonoverlapping laser pulse reduces the resistance by the same amount at each pulse. The resistor width being often in the order of the laser beam half-width, pulses are applied along the resistor’s length. Fig. 2 shows the lowering in parts per million (ppm) as a function of the laser fluence of a 4 µm × 40 µm 800-Ω resistor device following a single 300-ns
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Fig. 3. (a) Micrograph of the precision amplifier and (b) layout of the polysilicon-resistor pair R1 , R2 .
laser intervention. Results show that, using a single subthreshold irradiation, such a resistor device can be trimmed with a resolution as high as 200 ppm. The precision of the trimming is ultimately limited by the physical dimensions of the device. In the case of the long resistors employed in the present amplifier design, only a portion of the resistor need to be trimmed, achieving a precision below 100 ppm. The inset of Fig. 2 shows the high repeatability of the process. Knowing the resistance change induced by a single-pulse irradiation, it is thus possible to finely control the final resistance of a resistor device over a large range of values by simply repeating the trimming procedure at different locations on the device. The minimum distance between pulses greatly depends on the laser parameter used. Since very low sub-melting threshold-laser fluences are used, this trimming process affects the device only very locally, and a distance of 5 µm between the irradiation sites is sufficient. No damage is induced on structures surrounding the resistor.
IV. E XPERIMENTAL R ESULTS AND D ISCUSSIONS The proposed amplifier was fabricated in a Taiwan Semiconductor Manufacturing Company 0.18-µm single-poly six-metal CMOS process technology. The die micrograph of the fabricated operational amplifier with an on-chip bias circuit is presented in Fig. 3(a). The location and the size of the polysilicon resistors are shown. Resistor pairs are grouped for better matching. Interdigitated polyresistor structures, as shown in Fig. 3(b), are used for better matching, and there is no overhead involved in implementing the laser trimming technique, the only requirement being to avoid running metal lines on top. The resistor pair is composed of four 5-µm-large-by-80-µm-long fingers. Two dummy fingers are added on the sides. Five to ten laser pulses are required for the trimming, and considering a spot size of 2 µm in diameter, a maximum of only 4% of the total resistor area is affected; therefore, the thermal properties of the original polyresistor remain almost the same. The amplifier is designed to operate with a single-supply voltage VDD of 3.3 V.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 2, FEBRUARY 2011
Fig. 4. Measured untrimmed input offset voltage over the ICMR.
A. Measurement and Reduction of Input Offset Voltages The theoretical analysis detailing the resistors’ trimming sequence is detailed in [10] for a similar input stage designed with a bipolar transistor. Experimental results on the offsetvoltage reduction were obtained by performing laser trimming of resistors at the chip level. The amplifier was configured in a voltage follower setup with a gain of +1 V/V for the dc input-offset-voltage measurement. In this configuration, the input offset voltage was measured as the difference between the output and the noninverting input terminals over the entire ICMR. Since the offset voltage to be measured was in the range of microvolts after trimming, a high-resolution Keithley 2002 (K2002) precision multimeter with an 8.5-digit accuracy, which represents 10 nV on the lowest scale, was used for the purpose of obtaining dc measurements, and a Keithley 2400 (K2400) source-meter unit with a 5.5-digit accuracy was used to generate a dc ICM voltage ramp from 0 to 3.3 V with a specified number of steps. At each step, both input and output voltages are measured with the K2002 and are subtracted to obtain the offset voltage. Both K2400 and K2002 were connected through a general-purpose interface-bus cable and were interfaced to a desktop personal computer for data acquisition. The measured result for an untrimmed offset voltage over the ICM ranging from 0 to 3.3 V is presented in Fig. 4. The untrimmed input-offset-voltage curve lies approximately between +0.1 to +0.5 mV, meaning that the offset voltage due to the PMOS input differential pair is less than the NMOS input differential pair. This is consistent with the fact that the active area of PMOS input transistors ((W/L)M 3−M 4 = 2400 µm/1 µm) is larger than NMOS input transistors ((W/L)M 1−M 2 = 1600 µm/1 µm). As discussed in Section II, the effect of the threshold-voltage mismatch is proportional to the inverse of the transistor area. These transistors were implemented using tiled common-centroid layout techniques [12]. During the experimentation, five samples were tested, which showed a similar pattern of the untrimmed offset-voltage curve. The trimming is performed in two steps according to [10]. First (step 1), trimming is applied on R8 until VOS(P ) is made approximately equal to VOS(N ) . This step was performed at an ICM voltage of 0.45 V during which only the PMOS differen-
Fig. 5. Measured trimmed input offset voltage over ICMR after steps 1 and 2.
tial pair is active. The measured result is shown in Fig. 5, where VOS(P ) is almost aligned with VOS(N ) . The trimming sequence follows with an ICM voltage of 1.65 V (step 2), maintaining both differential pairs in an active state. During this step, the upper resistor R1 is selected for trimming, and the offset voltage at the midrail input value is reduced from +0.3 mV to −15 µV. The measured trimmed offset voltage after step 2 is also shown in Fig. 5. The final trimmed offset voltage lies between −30 and + 30 µV over the ICMR, where a part of this value is due to the noise injected from wires and the test equipment. The results presented in Figs. 4 and 5 are measured at an increment step of 10 mV for the ICM voltage sweep. Since the offset-voltage measurements are in the range of microvolts, several samples for each step are taken and averaged to reduce the effect of noise. Ten samples at each step were taken for the curve in Fig. 4, whereas 50 samples were used for the curves in Fig. 5 to increase the resolution. From the five tested samples, the worst trimmed scenario showed an offset voltage lying from −50 to + 60 µV over the ICMR. B. Measurement of Operational Amplifier Parameters Parameters of the amplifier were measured to determine its functionality after performing laser trimming. The transient measurements were obtained using an Agilent 33250A waveform function generator and a Tektronix TDS7154 oscilloscope. The amplifier was configured in a voltage follower setup with a capacitive load CL of 400 pF, a probe resistance ≥ 1 MΩ, and a probe capacitance ≤ 1 pF. These measurements were performed with a dc ICM voltage of 1.65 V. The measured response for a 3.7-VPP sine-wave input signal at 1.0 kHz is shown in Fig. 6. In this figure, the input sine wave extends ±0.2 V beyond the power rails. The output sine-wave response is clipping at 3.3 VPP , showing that the amplifier has a railto-rail I/O swing capability extending from the ground to the supply while driving a 400-pF load. The full-power bandwidth fFP of the amplifier is measured in a unity-gain configuration, and a sine wave of 3.3 VPP is applied at the input. The signal frequency is increased until the output signal shows some significant distortion. The measured fFP of the amplifier is 24 kHz. The unity-gain frequency fC is measured with an
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the noise during the measurement. The measured open-loop gain is at least 130 dB at 0.5 Hz. Several measurement results of the laser-trimmed rail-to-rail I/O operational amplifier are summarized in Table I for a capacitive load of 400 pF. V. C ONCLUSION A rail-to-rail I/O precision CMOS operational amplifier has been presented with experimental results proving the circuit functionality. An offset-reduction method has been successfully implemented with laser-trimmable polysilicon resistors in the standard CMOS process. An offset voltage varying from −30 to 30 µV over the ICMR has been obtained after trimming. Fig. 6. Measured response to an input sine wave of 3.7 VPP with the outputsignal clipping within 0- and 3.3-V supply limits (CL = 400 pF). TABLE I SUMMARY OF THE EXPERIMENTAL RESULTS FOR Cl = 400 pF
inverting closed-loop gain of 100 V/V where the frequency of a 3.2-VPP sine-wave input signal is increased until the measured amplitude of the output signal is equal to that of the input signal [17]. An fC value of 0.5 MHz was measured. The open-loop voltage gain AVOL , which is an important parameter of precision voltage amplifiers, is measured at 0.5 Hz, which is close to the dc operating point. The measurement is done in a closed-loop configuration similar to the ones used to characterize industrial precision amplifiers [4]. The oscilloscope bandwidth is limited to 20 MHz to minimize
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