A fuzzy logic inference processor

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 4, APRIL 1994

A Fuzzy Logic Inference Processor John W. Fattaruso, Member, IEEE, Shivaling S. Mahant-Shetti, Member, IEEE, and J . Brock Barton, Member, IEEE

Abstract-A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 pm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-massdefuzzification, may be computed in 2 ps.

I. INTRODUCTION

I

N recent years, fuzzy logic has become an accepted form in which to cast problems in control systems, robotics, and pattem recognition [ l]-[S]. Most applications rely on conventional digital microprocessors or microcontrollers programmed with a sequential calculation of the fuzzy logic quantities to perform the necessary logical inferences. This limits application to relatively low-speed problems. We feel it is inevitable that as fuzzy logic is employed in finding solutions to more problems, higher throughputs will be demanded of special purpose processing engines for fuzzy inferences [9]-[ 131. The highest throughput may be achieved by parallel processing, and indeed the computation necessary in a fuzzy inference lends itself naturally to the parallel execution of many simple components. However, since each computation component involves some multiplication and division, assuming a centerof-mass defuzification is performed, the use of exclusively digital circuitry for such a parallel architecture would quickly run into limits of chip area and power with very small numbers of rules, inputs, or outputs. There have been some all-digital parallel processing chips developed, but these generally make a significant sacrifice either in the speed or generality of the inference computation or in the size of rule set. Some realize fuzzification and defuzzification methods that are of limited use, or these are omitted altogether and left for a host processor to perform. The experimental processor chip described here is a mixed analog-digital inference engine with eight inputs and four outputs. The inference includes a full center-of-mass defuzzification. Because it calculates the results of 32 rules in parallel, its effective throughput can be orders of magnitude faster than that of a sequential processor. 11. PROCESSORFUNCTION

The processor interface behaves electrically like a static RAM. Input values, membership function contours and inference rules are programmed into dedicated memory locations Manuscript received August 20, 1993; revised January 10, 1994. The authors are with Texas Instruments Inc., Integrated Systems Laboratory, Dallas, TX 75265. IEEE Log Number 9216549.

by a master digital processor. The processor is designed to perform inferences over a set of 32 rules, each of which must be cast in the and-or form: If I, is F;j and I k is then 0, is G,

Fkl

and

. ..

and 0, is G,, and

. ..

where Ii is the ith input variable, 0, is the mth output variable, F;j is the jth membership function for the ith input is the nth membership function for the mth variable, and G, output variable. Each clause ‘‘I, is F+j” is called an antecedent, and each clause “0, is G,,” is called a consequent of a given rule. A fuzzy ‘or’ operation is implied between consequents of different rules that refer to the same output membership function. A start signal is sent to the fuzzy processor by writing into a particular address, and approximately 2 ps later the defuzzified output values that are the results of the inference may be read by the master processor out of other dedicated locations in the address space. The inference may be repeated with different input values by rewriting only the input values that need be updated and sending another start signal. Internally, the processing that occurs between memory locations is performed in the analog domain to exploit the attendant large savings in area. This economy of area allows a parallel computation of the entire rule set on one chip. A block diagram of the fuzzy processor may be found in Fig. 1. The eight, 8-b input values are stored in memory locations, and the range of each input variable may be covered by from one to seven membership functions, or fuzzy sets. All membership functions are assumed to be triangular or trapezoidal in shape. The 8-b coordinates of the four comer points that define each trapezoid are written into fixed memory addresses. For each input there are seven charge-redistribution digital-toanalog converters (DACs) that interpolate the value of the membership along the slope of the function contours. The result is an analog voltage that corresponds to the membership value p. The 56 analog membership values are sent to an array of circuit blocks that find the minimum voltage from among a set of up to 8 input voltages. The connections between the DAC outputs and the minimizer inputs are programmable by bit pattems loaded into memory locations. In this way 32 rules may be programmed into the processor. The operation of finding the minimum voltage level from among the input membership voltages for each rule is equivalent to determining the strength of a fuzzy logic rule evaluation from the logical ‘and’ operation between its antecedent clauses. The 32 rule strength voltages are fed to a similar array of blocks that find the maximum from among a set of up to 32 input voltages. Each rule may specify from one to four output

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 4, APRIL 1994

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8 input registers and 56 1.1 DACs

.....

56 /I values

-

L

Programmable array of 32 8-input minimum blocks

Programmable array

l

of 4 32-input maximum blocks

l 7

L I

32 rule strengths

Fig. 2.

-

I

Switched-capacitor DAC and membership function slope interpolator.

Fig. 1. Programmable fuzzy logic inference processor block diagram

variables as consequents, and each output variable may be decomposed into from one to seven membership functions. The selection of rules to drive each of the output membership functions is programmed by storing bit patterns in fixed memory locations. The operation of finding the maximum voltage from among a set of rule strength voltages corresponds to the fuzzy logical 'or' operation. The result from all the voltage maximizations are a set of 28 voltages that represent the heights of all the output membership functions. Finally, the 28 analog voltages representing output function heights are fed to four center-of-mass calculation circuits. These are extensions of switched-capacitor analog-to-digital converter (ADC) circuits that are arranged to perform the necessary analog division of two weighted sums of input voltages. The center coordinate and the average width of each output function must be available for this computation in dedicated memory locations. The trapezoidal shapes of the output functions are assumed to be symmetrical, which is equivalent to fuzzy singleton output functions. The resulting four 6-b digital words that represent the defuzzified output values may be read by the master processor out of fixed memory locations. 111. CIRCUITDESIGN Fig. 2 shows a simplified schematic of the membership value interpolation DAC. If an input value z is between two points PI and P, that define the beginning and end of the sloping region of a trapezoidal membership function, then the value of the membership that is to be interpolated is:

The DAC is a variable gain charge amplifier with the gain determined by the ratio of input capacitance to feedback capacitance. Each of these capacitances is set by the appropriate digital word by bit selection from binarily-weighted capacitor arrays. The output voltage from this DAC is ~ V R E Fwhere , VREF is an externally applied reference voltage.

Fig. 3 shows the design development of the circuit responsible for finding the maximum from among a set of input voltages. Consider first the array of source followers with a common load shown in Fig. 3(a). The common source output voltage will be an approximation to the maximum among the input voltages, but the precision is limited by the offset of V& between input and output, and the errors of resolving closely alike input voltages when two devices are conducting. If the simplified model of MOSFET behavior plotted in Fig. 3(b) is assumed, a first order analysis of these errors is straightforward. The characteristic plotted in Fig. 3(c) is the case where input voltage V, is assumed initially at a maximum and input VI is swept over its range. The ideal desired behavior of a maximizing circuit is also plotted. With typical device characteristics in a modern CMOS process, the error terms l o / g , and l / g m R are responsible for hundreds of millivolts deviation between the actual and ideal characteristic. The proposed precise, fully-differential version of this maximizer appears in Fig. 3(d). This same circuit will perform the minimization operation by reversing the sense of the differential voltage lines. The high-transconductance amplifiers in Fig. 3(d) have voltage gains of about 1000 and are designed with open-drain output drivers that will either source or sink output current. The current sources 10are small-valued sources necessary to keep one opamp in its high-gain region. In a manner similar to the array of source followers of Fig. 3(a), only the opamp corresponding to the maximum input voltage will be in its linear region and the rest will be saturated with no output current. The high loop gains in the circuit of Fig. 3(a) limit the characteristic error to a few millivolts. The center-of-mass calculator is shown in Fig. 4. This is an extension of a charge-redistribution ADC [14] in which the bits of the output digital word are found sequentially by binary search in the successive-approximations register (SAR). Before the conversion is started, however, the reference voltage to be used in the conversion process, VR,is accumulated by a separate charge amplifier as a weighted sum of the input height voltages Vhi. The weights are set by selection from binarily weighted capacitor arrays to Wi, the average width of the ith membership function. Then the charge that is converted

FATTARUS0 et al.: FUZZY LOGIC INFERENCE PROCESSOR

Assume V,

399

is maximum:

t

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v2

Characteristic

+

ideal as gm

+

m

(c)

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Fig. 3. (a) Single-ended low precision voltage maximizer, (b) Approximate MOSFET model for source follower array analysis. (c) Computation error of single-ended low precision maximizer. (d) Fully differential precision maximizer (or minimizer).

vhJ

Fig. 4.

\ Center-of-mass calculator (differential half-circuit).

by the ADC is arranged to be a different weighted sum of the same input voltages, this time weighted by W,C;, where Ci is the center coordinate of the ith membership function. The digital words W; and WiC; must be stored in on-chip RAM as part of the programming process. Since the output digital word of any ADC is the ratio of the effective input voltage divided by the effective reference voltage, this circuit can be used to calculate the ratio of weighted sums given in Fig. 4 that represents the center-of-mass location. The fuzzy logic inference chip was designed and fabricated in an 0.8-pm digital CMOS technology to achieve minimum wafer cost. All capacitors in the analog computation circuits are gate capacitances of PMOS devices. Approximately 2.5

Fig. 5. Opamps for minimum and maximum arrays.

V of DC bias is needed across these devices to ensure the voltage linearity of the gate capacitance is sufficient for 8 b of internal differential linearity. This bias is realized with a 2.5 V difference between input and output common-mode levels for each integration stage. Schematics for the opamps in the minimum and maximum cells and the opamp in the DAC and center-of-mass calculator are shown in Figs. 5 and 6, respectively. The comparator for the center-of-mass circuit is in Fig. 7. Note the switched-capacitor common-mode feedback in both Figs. 6 and 7. A die photo appears in Fig. 11.

Iv.

EST

RESULTS

Fig. 8 shows a family of measured differential output voltage waveforms (VOUTP- VOUTMof Fig. 2) of one of the

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vss Fig. 6 . Opamp for DACs and ADC reference voltage generators.

Fig. 7.

Comparator for center-of-mass calculator

input membership function DACs as it interpolates different membership values along the linear slope of a membership function. The four waveforms are generated with different values of the digital input value z loaded into the corresponding memory location. The analog reference levels were set to 1 V differential and the clock rate has been slowed to allow driving of wafer probe and oscilloscope probe capacitances. Fig. 9 is a family of differential ADC reference voltages measured from the chip. The reference voltage (V, of Fig. 4) represents the total mass of the output membership functions. The input membership functions and values were set so that all seven output membership functions had maximum analog

height. Then the digital input to the seven registers holding the output function widths were varied to generate this family. Width registers were either 0 or 255, and the number of registers that held 255 was varied between 1 and 7. This effectively varies the amount of mass over the output value range. Again linear dependence is shown in Fig. 9 between the generated reference voltage and the mass specified. The final measurement is of the digital center-of-mass calculation result from the successive approximation process. Again with full-scale analog function heights in effect, Fig. 10 shows a variety of measured comparator waveforms and output values. The comparator output voltage represents the sequence

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FATTARUS0 et al.: FUZZY LOGIC INFERENCE PROCESSOR

x = 64

h

>

EW,Ci=1785

1

v

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=

z = 48

c

3

n 3

0 0 0

0

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c

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0.5 0.0

CWiCi=1530

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CWiCi=1020

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’i EWiCi=973 n b

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\

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OUT=14

CLOCK

0

50

100 Time (psec)

150

200

CW,

50

100

150

200 250 300 350 400 450 500 Time (psec)

Fig. 10. Measured defuzzifier center-of-mass calculation.

Fig. 8. Measured input membership value interpolation

h

d

= 7 - 255

EWi = 6 . 255 a

EW,

1.0

0

50

100

150

= 5 . 255

200 250 Time (psec)

300

350

400

450

500

Fig. 11. Fuzzy logic inference processor chip photomicrograph.

Fig. 9. Measured defuzzifier total mass calculation.

ACKNOWLEDGMENT of bits accumulated in the center of mass value, and the output value was that read from the appropriate memory location. The contents of the seven registers holding the (width).(center coordinate) of the output membership functions were varied to represent wide-ranging relocation of the functions over a range of output values. The sum of all the registers is given in the figure for each trial, and the computed center of mass varies accordingly.

V. SUMMARY

This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. A center-of-mass defuzzification in included. Simulations predict a computation time for the array of about 2 psec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 b. The completed chip measures 7mm by lOmm in an 0.8 pm CMOS technology. Test results prove functionality of the processing circuitry. Further testing is planned to verify the overall computation linearity of the processor.

The authors wish to acknowledge the contributions of P. Thrift, A. Penz, and A. Katz to the system design of this processor chip. Layout support was provided by D. Franck, test support contributed by R. Hardin.

REFERENCES L. Zadeh, “Fuzzy sets,” in Information and Control, vol. 8. New York: Academic, 1965, pp. 338-353. L. Zadeh, “Outline of a new approach to the analysis of complex systems and decision processes,” IEEE Trans. Syst., Man, Cybern., vol. 3, no. 1, pp. 2 8 4 5 , Jan. 1973. S.-G. Kong and B. Kosco, “Adaptive fuzzy systems for backing up a truck-and-trailer,” IEEE Trans. Neural Networks, vol. 3, no. 2, pp. 211-223, Mar. 1992. T. Yamakawa, “A fuzzy inference engine in nonlinear analog mode and its application to a fuzzy logic control,” IEEE Trans. Neural Networks, vol. 4, no. 3, pp. 496522, May 1993. G. Kaplan, “Industrial electronics: Fuzzy logic controls,” IEEE Spectrum, vol. 28, no. 1, p. 59, Jan. 1991. D.Conner, “Designing a fuzzy-logic control system,” EDN, vol. 38, no. 7, pp. 76-88, Mar. 31, 1993. D. Brubaker, “Everything you always wanted to know about fuzzy logic,” EDN, vol. 38, no. 7, pp. 103-106, March 31, 1993. G. Legg, “Transmission’s fuzzy logic keeps you on track,” EDN, vol. 38, no. 26, pp. 60-63, Dec. 23, 1993. H. Watanabe, W. Detlof, and K. Yount, “A VLSI fuzzy logic controller with reconfigurable, cascadable architecture,” IEEE J . Solid-state Circuits, vol. 25, no. 2, pp. 376382, Apr. 1990.

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[lo] M. Sasaki, T. Inoue, Y. Shirai, and F. Ueno, “Fuzzy multiple-input maximum and minimum circuits in current mode and their analyses using bounded differential equations,” IEEE Trans. Compur., vol. 39, no. 6, pp. 768-774, June 1990. [ 1I] M. Togai and H. Watanabe, “Expert system on a chip: An engine for real-time approximate reasoning,” IEEE EXPERT, vol. 1, no. 3, pp. 55-62, Aug 1986. [ 121 Product Manual, “NLX230 Fuzzy Microcontroller.” American Neuralogix, Inc., July 1991. [ 131 Product Manual, “FP-3000 Digital Fuzzy Processor,” OMRON Electronics, Inc., 1991. [14] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analogto-digital conversion techniques-Part I,” IEEE J. Solid-state Circuirs, vol. SC-IO, no. 6, pp. 371-379, Dec. 1975.

John W. Fattaruso (S’75-M’84) was bom in Iowa in 1956 and grew up in Berkeley, CA. He received the B.S. (highest honors), M.S., and Ph.D. degrees in electncal engineering from the University of California, Berkeley, through 1986. He has been a Hertz Foundation Fellow, Teaching Associate, Research Assistant, and Instructor at the University of Califomia, Berkeley. In 1979 he worked in the Digital Signal Processing R&D group at Hewlett-Packard, Santa Clara, CA, and in 1985 he served as a consultant to Seeq Technology, San Jose, CA. Since 1987 he has been with the Components R&D department of Texas Instruments, Dallas, TX,workmg on MOS analog VLSI technology in the Integrated Systems Lab. He was elected Senior Member of the Technical Staff in 1994. His research interests include analog circuit design, circuit simulation and optimization, neural networks, and numencal analysis. He currently holds five patents in circuit design. Dr Fattaruso is a member of Eta Kappa Nu, Tau Beta PI, and Phi Beta Kappa.

ShivalingS. Mahant-Shetti (S’72-M’77) received the B.Tech. (Hons) degree in electrical engineering from the Indian Institute of Technology in Bombay, India, in 1972 and the M.Sc. and Ph.D. degrees in electrical sciences from Brown University in 1975 and 1977, respectively. Since joining Texas Instruments (TI) in 1982, he contributed to many projects including the design and test of the 72 K VHSIC sRAM, programmatic generation of the submicron CMOS testchips, statistical parametric data analysis and design rule synthesis (SPADS), 32-b LISP chip design and debug, successful commission of the first MegaOne tester at TI, and parametric testing for EPIC1 technology. He was elected a Senior Member of the Technical Staff in 1987 and managed the Design Engineering Branch (1987-1989). In 1989 he went to TI (India) to set up the Lin-ASIC design center. In 1990, he retumed to SPDC as the Branch Manager of the Technology and Circuit Characterization Branch, where he was responsible for 0.5 g m technology design issues, parametric testing, functional testing, SPICE model verification and delivery, and electron beam based parametric and functional testing. His interests included study of interconnect resource calculations and CMOS technology scaling and manufacturability issues. Since 1992, he has concentrated on design issues. he designed memory and digital parts of fuzzy logic and clustering chips. He was also involved in the development of a base cell for dense gate arrays. Currently he is working on low power CMOS circuit issues. He has published over 25 papers, holds 9 patents, and has over 20 patent applications pending.

J. Brock Barton (M’72) received the Ph.D. degree in solid-state physics from M.1 T. in 1972. He is a Texas Instruments (TI) Fellow in the Integrated Systems Lab of TI’s Components R&D organization. His current responsibilitles include managing development of ultra-low power integrated circuit design techniques, and CAD tools for facilitating these methods He was responslble for the design of TI’s first standard cell library. He joined TI in 1972 and has worked in TI’s Equipment Group, Central Research Laboratories, Semconductor Group, and Semiconductor Process and Design Center (SPDC), now called Components R&D. He has worked on a number of different programs, including CCD imager and memory design and development, CMOS calculator chip product engineenng, and MOS memory and microprocessor process development, prior to helping create TI’s ASIC technology. More recently, he was responsible for fuzzy logic IC development in SPDC. He is the author or coauthor of more than 25 technical papers and publications, and holds 5 patents.