A capstone computer engineering design course

288

IEEE TRANSACTIONS ON EDUCATION, VOL. 42, NO. 4, NOVEMBER 1999

A Capstone Computer Engineering Design Course William D. Richard, Member, IEEE, David E. Taylor, and David M. Zar, Member, IEEE

Abstract— This paper describes the senior computer engineering capstone design course at Washington University in St. Louis. As part of this course, three-student teams develop a complete 8-bit microprocessor using a hardware description language (VHDL) and implement their designs in a small FPGA. Programmed FPGA’s are “booted” at the end of the course and tested for accuracy. Students also write an assembler or a simple calculator for their microprocessor. This paper describes the microprocessor architecture and tool flow used in the course. Index Terms—Capstone design course, FPGA, microprocessor, VHDL.

I. INTRODUCTION

T

HIS paper describes the senior computer engineering capstone design course at Washington University in St. Louis, EE/CS 462: Digital Computers III. The first portion of the course covers the details associated with arithmetic logic unit (ALU) design, including various ways to construct adders, subtractors, multipliers, and dividers. Topics covered include look-ahead carry adders, Wallace trees, etc., with the focus on possible tradeoffs between size and speed. The first portion of the course also introduces the very high speed integrated circuit (VHSIC) hardware description language (VHDL) [1]–[4]. The course text, “VHDL Made Easy!” by Pellerin and Taylor [5], focuses on the development of synthesizable VHDL. The Mentor Graphics QuickHDL compiler, qvhcom, is used for compilation, and the Mentor Graphics QuickHDL simulator, qhsim, is used for simulation [6]. After studying ALU design and learning VHDL, students are introduced to the target microprocessor architecture being developed during the current semester. Several weeks are spent studying the architecture, instruction set, and general operation of the microprocessor. Discussions are held on how best to implement various architectural features. In the project portion of the course, three-student teams design and implement the target 8-bit microprocessor in a small Actel field programmable gate array (FPGA) [7] using VHDL. After rigorous simulation, final designs are synthesized using the Exemplar Leonardo [8] tool. Place and route functions are implemented using the Actel Designer Series software [9]. Both the Mentor Graphics and Actel tools are part of the Mentor Graphics and Actel educational programs. After programming the FPGA, each microprocessor is installed in a small computer system developed by the instructor and 6 in. computer system “booted.” The schematic for the 4 board is shown in Fig. 1. The system board contains 32 768 Manuscript received December 4, 1998; revised July 2, 1999. The authors are with the Department of Electrical Engineering, Washington University, St. Louis, MO 63130 USA. Publisher Item Identifier S 0018-9359(99)09160-8.

bytes of EPROM storage, 32 768 bytes of SRAM storage, a UART, an RS-232 driver, an oscillator, and two “glue logic” PAL’s. The overall project is completed during the last eight weeks of the three-semester-hour 15-week course. During the project portion of the course, lectures are used to discuss design issues and to continue development of processor architecture details. The concepts of logic synthesis and FPGA place and route are also discussed in detail. Weekly halfhour team meetings are held with the instructor, and weekly milestones are checked for completion. During the last week of the semester, final student designs are programmed into the target FPGA and tested for functionality. II. TARGET MICROPROCESSOR ARCHITECTURE The block diagram of the microprocessor developed during the Spring 1998 semester is shown in Fig. 2. This architecture is an extension of the architecture presented by Ivan Tomek in his text “The Foundations of Computer Architecture and Organization” [10]. Several features have been added to the original architecture, including a stack pointer and indirect register, for stack, indirect, and indexed addressing. The individual components are: • arithmetic logic unit (ALU); • condition code register (CCREG); • accumulator (AC); • instruction register (IR); • controller (CONTROL); • program counter (PC); • data counter register (DC); • Indirect Register (IND); • Stack Pointer (SP); • address register multiplexor (XYZMUX); • address bus multiplexor (ABMUX); • address increment/decrement module (INCDEC); • data bus buffer (BUSBUFFER); • data bus multiplexor (DATAMUX); The instruction set for the microprocessor is shown in Table I. The 71 instructions are broken into eight groups based on “address mode”: implied, immediate, absolute, indirect, indexed, stack, I/O, and jump. There are, for example, five different ADD instructions (with implied, immediate, absolute, indexed, and stack addressing modes). Table II. lists the operation codes (OP codes) for each instruction. Table III documents the action associated with each instruction and the affect each instruction has on the five flags in the CCREG: half carry (H), carry (C), negative (N), overflow (V), and zero (Z). As seen in Fig. 2, the target microprocessor is a simple load/store microprocessor with one accumulator register, AC.

0018–9359/99$10.00  1999 IEEE

RICHARD et al.: CAPSTONE COMPUTER ENGINEERING DESIGN COURSE

289

Fig. 1. Computer system board schematic.

The microprocessor has an 8-bit external data bus and a 16-bit external address bus. Program execution, at reset, starts at address 0000H. At reset, the PC is reset to 0000H, and the controller sets the ABMUX to gate the PC output to the external address pins. The ABMUX can also be used to select the SP output for stack-based instructions, the IND for indirect instructions, or the DC for absolute, indirect, and indexed instructions. The INCDEC block is used to increment and decrement addresses from the four address registers (PC, DC, IND, and SP). The PC, DC, IND, and SP are implemented as simple registers to reduce the total number of logic modules required for these functions. This optimization was necessitated by the limited number of logic modules available in the target FPGA. The microprocessor has 29 nonpower/ground pins: 16 address lines (A[15:0]), eight data bus lines (D[7:0]), a clock pin (CLK), a true low reset pin (RESET_L), a data transfer pin (DTR), a read/write pin (R_W_L), and a pin used to distinguish between memory and I/O transfers (IO_MEM_L). In addition to the 64-Kbyte memory address space, the processor also has a 256-byte input–output (I/O) address space, and the IN and OUT instructions are used to address peripherals mapped into this address space.

Two-operand arithmetic and logical operations use the contents of the AC register and either an immediate-, absolute-, indirect-, indexed-, or stack-addressed operand. Immediate operands are stored in memory immediately following the OP code. Absolute operand addresses follow the OP code in memory, with the high byte of the 16-bit address stored first. Indirect addresses (the address of the address) are also stored immediately after the OP code (high byte first). The control block is implemented as a six-state Mealy model finite state machine (FSM). Fig. 3 shows the state diagram for the FSM. In state S0, the next OP code is fetched from memory and stored in the IR. States S1 through S5 assert the 41 control signals produced by the CONTROL block so that proper instruction execution is performed. III. VHDL IMPLEMENTATION Each three-student team develops VHDL entities and architectures for each of the blocks shown in Fig. 2 and simulates them for accuracy. Simple blocks such as the program counter are coded first. The controller, by far the hardest block to code, is developed last. Fig. 4 is a Gantt chart showing the weekly schedule for the project portion of the course. During weekly meetings,

290

Fig. 2. Microprocessor block diagram.

IEEE TRANSACTIONS ON EDUCATION, VOL. 42, NO. 4, NOVEMBER 1999

RICHARD et al.: CAPSTONE COMPUTER ENGINEERING DESIGN COURSE

291

TABLE I MICROPROCESSOR INSTRUCTION SET

Fig. 3. Control block finite state machine.

student groups present their code and simulation results to the instructor for review. The instructor checks the VHDL code and simulation results for accuracy and provides feedback on possible improvements. Currently, the Mentor Graphics VHDL tool qvhcom is used for VHDL compilation. The Mentor Graphics tool qhsim is used for interactive simulation of each individual block. After each individual block is coded and tested, student teams develop a structural VHDL program that “wires” each of the individual blocks together to form the final microprocessor. IV. MICROPROCESSOR SIMULATION TESTBENCH A rather complete simulation testbench has been developed for microprocessor simulation. This testbench consists of: a VHDL EPROM model, a VHDL SRAM model, a VHDL

UART model, and an overall VHDL structural “testbench” that wires the microprocessor, EPROM, SRAM, and UART together for simulation. The testbench emulates the operation of the target processor board on which final microprocessors will be tested. It maps the EPROM starting at address 0000H in the address space, the SRAM starting at address 8000H in the address space, and the UART starting at address 00H in the I/O address space. Initially, the instructor-supplied behavioral EPROM model holds a sample calculator program that can be executed by the microprocessor during simulation. A program written in C, “makeprom,” was used to generate the VHDL description of the EPROM from an executable binary file. This executable binary file was generated from a source assembly language file by an assembler written in C called “toyasm.” The behavioral SRAM model has 32 768 bytes of “SRAM” for use as temporary storage. The UART model currently allows characters written to the UART to be displayed on the workstation screen (using stdio). This has been found to be extremely useful in debugging student designed microprocessors. The overall microprocessor simulation flow is shown in Fig. 5. The first path shows the compilation of the “toy.vhd” file containing the structural description of the microprocessor generated by the student teams. The second path shows the compilation of the “bigsram.vhd” file containing the SRAM description, and the third path shows the compilation of the “safeuart.vhd” file containing the UART description. It is possible to edit the UART description to change the input stimulus provided by the testbench. Text entry from the workstation is currently under development and planned for use in future versions of the course. As shown by the dashed ellipses in Fig. 5, students can generate their own calculator program (which they are required to write as part of the course). After coding their calculator in assembly language, students assemble their calculator using either the supplied assembler (toyasm) or one they have written. They then use the makeprom utility to generate a behavioral VHDL EPROM description from the object file produced by the assembler. Optionally, students can write their own test program, and this path is shown in Fig. 5 on the right side of the flow. A similar process is used to generate a behavioral EPROM description that can be used to exercise the microprocessor using the testbench.

292

IEEE TRANSACTIONS ON EDUCATION, VOL. 42, NO. 4, NOVEMBER 1999

Fig. 4. Project schedule in Gantt chart form. The XYZMUX and INCDEC were coded as part of the PC, DC, and SP. The code for the BUSBUFFER block was supplied.

Fig. 5. Microprocessor simulation flow.

RICHARD et al.: CAPSTONE COMPUTER ENGINEERING DESIGN COURSE

TABLE II MICROPROCESSOR OPERATION CODES: OPCODE “INSTRUCTION” “GROUP.” EXAMPLE: ADD ABSOLUTE 00 001 010

=

=

AND

V. SOFTWARE VI. SYNTHESIS, PLACE AND ROUTE,

AND

BACK ANNOTATION

After simulation, student teams synthesize their designs using the Exemplar Leonardo synthesis tool using a supplied script. Several class periods are taken to describe the synthesis process, but students are not currently required to become experts in the use of the tool. They do, however, learn to in-

293

TABLE III INSTRUCTION EXECUTION RESULTS: INDICATES FLAG UPDATES, 3 INDICATES FLAG DOES NOT CHANGE, AND R INDICATES FLAG IS RESET TO ZERO

+

terpret the output of the synthesis tool and extract information regarding the number of logic modules used, etc. After synthesis, the ACTEL Designer Series software is used with another supplied script to place and route the student designs in an Actel 1020B FPGA. This FPGA has 547 logic modules, and, incidentally, is the second smallest Act 1 series FPGA marketed by Actel (only the 1010B is smaller in terms of the total number of logic modules with 295). After place and route, the Designer Series software is used to generate a structural VHDL file and a standard delay format (SDF) file for post place-and-route simulation. In addition to post place-and-route simulation, which is performed using the Mentor Graphics qhsim tool, the Designer Series tools are used to determine the maximum microprocessor speed possible via path analysis. As mentioned above, each student team is required to write either an assembler for their microprocessor or a simple twofunction (add/subtract) calculator (in assembly language) as part of their project requirements. Since the course typically has a mix of EE, CS, and CoE (Computer Engineering) students, different groups feel more comfortable, typically, with one or the other. At the end of the semester, student-written assemblers are tested by the instructor for accuracy, including the use of

294

IEEE TRANSACTIONS ON EDUCATION, VOL. 42, NO. 4, NOVEMBER 1999

these assemblers to assemble the supplied calculator program. Student-written calculators are actually downloaded to a working microprocessor and executed. These calculators have all run in the testbench prior to this, and there has never been a case of a calculator working correctly in simulation and not on the actual hardware. VII. RESULTS EE/CS 462M has been structured as described above for three semesters. Prior to this, the same course was taught once using a mixture of VHDL and schematic capture to implement a simpler version of the microprocessor described here. During the first two semesters, all but one or two of the eight–ten student designs “booted” when placed on the processor board and power applied. Most recently (Spring 1998), six of nine student designs simulated correctly in the testbench. Only one of these designs, however, actually fit into the FPGA due to size constraints. A considerable amount of time was used in class discussing methods for reducing overall microprocessor size since it was anticipated that size would be a constraint. Of the five designs that worked in simulation but were too large to fit in the FPGA, most were too large by less than ten logic modules. The three designs that did not simulate correctly had one or more instructions that did not execute properly. VIII. CONCLUSIONS EE/CS 462M takes students through a modern design flow, starting with a textual description of the target microprocessor and ending with a working “product.” They learn VHDL, simulation, and the concepts associated with synthesis, place and route, path analysis, and back annotation. Along the way, they use many of the concepts they learned in earlier computer engineering courses, including logic design, computer architecture, programming, and software engineering. The development of a course like EE/CS 462M represents an enormous amount of effort on the part of the instructor and staff. This effort pays off, and the result is a wonderful capstone design experience for senior computer engineering students. Students with this background have received top salary offers from companies upon graduation, and many are so proud of what they have accomplished that they want to take copies of their microprocessors to job interviews and with them when they graduate. Much of the material developed for EE/CS 462M is available for use at other institutions participating in the Mentor Graphics and Actel educational programs. It is our hope that other students can benefit from the effort described here.

ACKNOWLEDGMENT The authors would like to thank the Mentor Graphics and Actel educational programs for the support they have supplied during the development of EE/CS 462M. Specifically, the authors would like to thank J. Wetch at Actel for his tireless assistance with issues related to the Actel tools during the development of the current design flow and J. Schroeder, manager of the Mentor Graphics Higher Education Program. REFERENCES [1] Standard 1076-1993, IEEE Standard VHDL Language Reference Manual, IEEE, 1994. [2] Standard 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability, IEEE, 1993. [3] Standard 1076.3, VHDL Synthesis Packages, IEEE, 1995. [4] Standard 1076.4, VITAL ASIC Modeling Specification, IEEE, 1995. [5] D. Pellerin and D. Taylor, VHDL Made Easy! Englewood Cliffs, NJ: Prentice-Hall, 1997. [6] Mentor Graphics Corp., Getting started with QuickHDL and VHDLwrite, Nov. 1996. [7] Actel Corporation, Actel Data Book and Design Guide, Spring 1998. [8] Exemplar Logic, Inc., Leonardo Synthesis and Design Guide, Release 4.0, 1996. [9] Actel Corporation, Actel Designer Series Development System User’s Guide, Version R1-1998, 1998. [10] I. Tomek, The Foundations of Computer Architecture and Organization. Rockville, MD: Computer Science, 1990.

William D. Richard (S’80–M’88) received the B.S., M.S, and Ph.D. degrees in electrical engineering from the University of Missouri, Rolla, in 1983, 1985, and 1988, respectively. He is a Professor of Electrical Engineering at Washington University, St. Louis, MO. He was responsible for the development of EE/CS 462.

David E. Taylor received the B.S. degree in electrical engineering and the B.S. degree in computer engineering from Washington University, St. Louis, MO, in 1988. He was a student in the Spring 1998 section of EE/CS 462 and a member of the team that generated the microprocessor design small enough to fit in the target FPGA. He is currently a Graduate Research Assistant in the Applied Research Laboratory at Washington University. He has also performed a summer project, funded by the Mentor Graphics Higher Education Program, to develop a generic FPGA design flow and an FPGA flow for future EE/CS 462 courses using the Mentor Graphics WorkXpert tool.

David M. Zar (S’89–M’93) received the B.S. degree in electrical engineering and the B.S. degree in computer science and the M.S. degree in electrical engineering from Washington University, St. Louis, MO, in 1992 and 1993, respectively. He is a member of the technical staff of the Department of Electrical Engineering at Washington University in St. Louis. He assisted with the development of the target computer board and many of the associated course materials.