A 3.2 mW 0.13 µm High Sensitivity Frequency-domain CMOS Capacitance Interface

A 3.2 mW 0.13 µm High Sensitivity Frequency-domain CMOS Capacitance Interface Javed S Gaggatur

Pradeep K Dixena

Gaurab Banerjee

Electrical Communication Engineering Indian Institute of Science Bangalore, 560012, INDIA [email protected]

ANURAG DRDO Hyderabad, 560012, INDIA [email protected]

Electrical Communication Engineering Indian Institute of Science Bangalore, 560012, INDIA [email protected]

Abstract—A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The timeperiod difference of two such oscillators is compared and is readout using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. The capacitance sensor interface system was designed and a prototype was implemented in a 0.13 µm standard CMOS technology. Experimental and simulation results are presented. It exhibits a maximum sensitivity of 8.1 mV/fF, which is significant improvement over the state-of-the-art while consuming 3.2 mW from a 1.2 V supply.

I. I NTRODUCTION Capacitive sensors exhibit a change in electrical capacitance in response to changes in physical stimuli like displacement, area and dielectric properties. The range of application for capacitive sensors is from commercial, industrial and defence to space sector [1]–[4]. These versatile sensors offer higher precision and robustness, simpler construction and lower power than resistance based alternatives but require more complex interface circuits. In many cases, the gap between the two electrodes of a capacitive sensor changes during the operation making the measurement non-linear as the sensitivity is inversely proportional to the gap. To reduce the sensor interface complexity, it is desired to reuse a given circuit topology for several applications and adjust the sensing range and sensitivity for each particular application [3]. Depending on sensor and the application, the capacitance value can change from femto-farads to tens of picofarads, making the design of such circuits challenging [5]–[7]. The primary objective of this work is to design a capacitive sensor interface circuit with high sensitivity and low noise. To achieve this goal a frequency domain implementation is used which is less sensitive to amplitude noise. In this work, a current controlled ring oscillator (CCRO) topology is used for capacitance to frequency conversion and it is optimized for linearity, area, power and noise performance. The interface circuit is able to measure the capacitance change to a resolution a 10f F with a nominal capacitance of 10pF . II. P ROPOSED C APACITANCE I NTERFACE S YSTEM Fig. 1 describes the frequency domain capacitance interface system (CIS) architecture, which provides a capacitance to voltage conversion and a direct digital conversion. This architecture uses two steps: the first step is to convert the change

Sensor

Capacitance to Period

Period to Voltage Information in period

Cref Csens PFD

CP

Sensor

Capacitance−Controlled Oscillator

Period−to−Voltage Converter

Fig. 1. System level architecture of the proposed system.

Fig. 2. Frequency spectrum of the measuring system.

in capacitance to a change in frequency, as shown in the frequency spectrum in Fig. 2. In the second step, the change in frequency is sensed and converted it to an analog voltage using a phase frequency detector (PFD) and charge pump (CP). This work also shows that frequency domain implementation provides good sensitivity and resolution compared to the other architectures. The overall sensitivity of the CIS is given by Soverall =

∂Vout Icp M Vosc = DN (N + 1) ∂Cdif f Ccp Ib

(1)

where D is the division ratio, N equivalent to the measuring duration, Icp is the current to the charge the capacitance Ccp in the charge pump, M is the number of stages in the CCRO, Vosc and Ib are the maximum amplitude and the bias current of the CCRO output, respectively. The sensitivity of the CIS is spread over two stages. The input stage sensitivity corresponds to the capacitance (Cdif f ) to time period (Tdif f ) conversion, defined as the time sensitivity and the output stage sensitivity deals with the time period-to-voltage (Vout ) conversion, and defined

Fig. 3. Effect of the sensor output frequency to bias current and capacitance change. Highlighted region for linear and optimized performance for femto farad capacitance measurement.

Fig. 4. Sources of noise occurring in ring-oscillator based frequency measurement systems. Ref f models the effective loss in the system. Cef f is the effective capacitance at that node incl. the sensing capacitance.

as voltage sensitivity. Both, play a key role in determining the overall sensitivity of the system. The oscillators interface the external sensor/reference capacitance to the internal circuits. A CCRO was chosen as it provides a linear relationship between the time period of the oscillator signal and a change in the sensor capacitance, while occupying less area and consuming less power in comparison with inductance based systems. They are also scalable with modern CMOS processes. The CCRO is optimised for a sensitive and linear operation around a nominal capacitance Cnom , governed by (1). Fig .3 shows the sensitivity of the CCRO to the change in input capacitance and bias current. The frequency of oscillation varies inversely with capacitance change and directly with bias current (1). The resolution of the detected input capacitance depends on the CCRO output frequencies of two oscillators, fref (=1/Tref ) and fsens (=1/Tsens ) (Fig. 2). The equivalent number of bits of the conversion of this interface is fref .fsens (2) nsensor = 2n = τc fref − fsens

at the supply node of the oscillator. This reduces the effect of PVT variations on the frequency measurement and hence, the resolution of the system.

where n is the number of bits of the converter and τc is the time-change due to sensor capacitance. Considering that the relation between the sensor and reference oscillator frequencies is determined by the parameter β, with 0 < β < 1, fsens = (1 − β)fref and thus, the number of bits in (2) can be expressed as nsensor

(1 − β)fref fsens = 2n = τc . = τc β β

(3)

The resolution depends inversely on the minimum time delay of measurement. The relation between the reference and sensor oscillator for minimum power consumption was found to be around β = 0.01 [4]. It has also been considered that low oscillator frequencies help reduce the power consumption and the effect of parasitics, but it implies having a longer measurement time. Therefore a frequency that provides a compromise between measurement time and power consumption is required in order to optimize the converter’s performance. It has been determined for the reference oscillator that for a power supply of 1.2 V, it oscillates around 20 MHz and fulfills the requirements of the system. The reference CCRO is injection locked externally, by injecting an at-frequency signal

A. Noise sources in Oscillator-based Sensor The noise sources present in the CIS that affect the system during measurement are shown in Fig. 4. The sensor front end has been modeled as the RC circuit with the ring oscillator at its core. The major sources of noise in this system are supply voltage variation, ground bounce in the system, noise current in the devices, temperature variation over measuring range and the time-delay mismatch in the differential sensors. They are classified and tabulated as shown in Table I. Assuming all the noise sources are uncorrelated, the normalized frequency detection sensitivity within the measuring bandwidth can be expressed as [8] Z +∞ h ωτ i 4 2 σ ∆f (τ ) = dω [Sφ,osc (ω) + Sφ,env (ω)]sin2 2 2 f0 πω0 τ 0 2   1 2 2 2 2 (τ ) + σ (τ ) + σ σ (τ ) + σ = (τ (4) ) ∆Supp ∆T emp ∆tdN tdN T emp Supp τ 2 osc 2 2 2 σ ∆Supp (τ ) = σ ∆V DD (τ ) + σ ∆GN D (τ ) V DD

Supp

GN D

Let the cumulative jitter due to the factors mentioned in Table I be Tjit . The effect of jitter on sensitivity is given as, S

S 0 time

= Stime (1 − Tjit /Tdif f )

0

= Soverall (1 − Tjit /Tdif f )

overall

(5)

Jitter reduces the overall sensitivity and the resolution of the measuring system by a factor (Tjit /Tdif f ). III. C IRCUIT D ESIGN AND I MPLEMENTATION A. Capacitance-to-Frequency Conversion The oscillators interface the external sensor/reference capacitance to the internal circuits.The oscillator has a three-stage current controlled ring topology (M1 -M6 ) and the current control Ib is carried out using Rs , as shown in Fig. 5. A 2-input NAND gate with an enable signal (EN), from CSL, is used to synchronize the sample signal. The ring oscillator output is connected to a D flip-flop to sharpen the rising edge and to maintain a 50% duty cycle at the oscillator output.

TABLE I N OISE SOURCES IN R ING O SCILLATOR - BASED CAPACITANCE SENSORS Noise Source σ 2∆V DD

Description Supply Variation

V DD

σ 2∆GN D σ2

Ground Bounce

GN D

∆T emp T emp

Summary

Phase Noise

Measuring Environment Noise

Environment related phase noise Sφ,env(ω)

Thermal Noise Differential Delay Mismatch

Oscillator Phase Noise Sφ,osc(ω)

Temperature Variation

2 σ∆R/R

Circuit Losses

2 σtdN

Time-delay variation

Accumulated Jitter σ 2∆V DD (τ ) + σ 2∆GN D (τ ) + σ 2∆T emp (τ ) V DD

GN D

T emp

2 σ 2∆R (τ ) + σtdN (τ ) R

Fig. 5. Current controlled ring oscillator with embedded capacitance sensor

Fig. 7. Schematic of the phase frequency detector and the charge pump.

Fig. 6. On-chip digitally tunable embedded capacitor Csens including the nominal capacitor Cref .

Fig. 6 shows the details of an on-chip digitally tuned capacitor, which is used for testing and in calibrating the system for PVT variations. The operating frequency is tuned by changing the value of capacitance. The selection of the control bits is done using a scan interface controlled by the CSL block. During calibration, a delay correction is done to remove the delay difference in the two paths. To enhance the dynamic range and to increase the sensitivity of the sensor a mod-10 synchronous counter-based frequency divider, each having a division ratio D, is used in each path.

current source as shown in Fig. 7. The error due to current mismatch and skew in the pulses is mitigated. The current source can be tuned for sensitivity and acquisition time, at the cost of higher noise. The PFD and CP are reset at the end of every conversion. C. Control and Synchronization Logic (CSL) To synchronize the complete system, a fully digital samplelogic block was designed with a sample clock signal as an input. The outputs from this block are used to generate synchronization signals for the oscillators and PFD (EN) and the charge pump (RST). It also generates a sample out signal which indicates the end of conversion that helps in interfacing with an external ADC.

B. Frequency-to-Voltage Conversion The phase frequency detector (PFD) compares the phase of the sensor and the reference oscillator outputs and generates pulses (UP), commensurate with the differences in phase. For this application, a 3-state digital PFD is chosen over other architectures (Fig. 7), as it is edge sensitive, and therefore, independent of the duty cycles of the input signals [3], [9]. The charge pump (CP) (Fig. 7) is an important building block of the interface system. It converts the time period difference of the two oscillators into a voltage. So the linearity of the measurement technique depends on this block. In this architecture, we have proposed a novel charge pump, which operates only for the UP output of the PFD and uses a single

IV. M EASURED R ESULTS The CIS was designed and implemented in 0.13 µm standard CMOS process, as shown in Fig. 8 and it is powered by a 1.2 V supply. To reduce the offsets, the critical paths and oscillator outputs are laid out to be symmetrical. Further, coupling from the power supply and the substrate induces offsets in the measurement. To protect the critical blocks from such interactions, guard rings and isolated supplies are extensively used. Fig. 9 describes the measurement flow and the initial calibration methodology followed to obtain the output voltage Vout . Fig. 10 shows output of the system for varying nom-

TABLE II C OMPARISON OF THE PROPOSED CMOS S ENSOR WITH REPORTED STATE - OF - THE - ART I NTEGRATED S ENSORS . Parameter Sensitivity (mV/fF) Technology (µm) Supply (V) Power (mW) Area (mm2 )

Fig. 8. Capacitive Interface System (a) layout and (b) photograph

This Work 8.1 0.13 1.2 3.2 0.17

[4] 0.3 0.35 ±1.65 7.9 0.47

[10] 0.83 0.35 3.3 1.44 0.048

[11] 0.09 0.35 5 50 6.25

[12] 4 0.5 3.3 0.001 0.078

[5] 5 0.7 5 7 2.66

8.1 mV/fF can be achieved, while consuming 3.2 mW from a 1.2 V supply, allowing the measurement of femto farads of capacitance. The system performance can be reconfigured for specific applications using the choice of a set of variables, such as the charge pump current, integration time, and the division ratio, some of which require a tradeoff between precision and measurement time. The sensitivity of femto Farads, enables its use in precision applications including biomedical diagnostics and navigational systems. ACKNOWLEDGEMENT The authors would like to thank the members of Analog and RF Systems Laboratory (ARSL) for the technical discussions. We gratefully acknowledge the financial support provided by the Department of Electronics & Information Technology (DeitY), Government of India. R EFERENCES

Fig. 9. Flowchart showing the measurement flow for the system with the calibration.

inal capacitance values having a sensitivity of 20.3 mV/pF. To enhance the sensitivity and to narrow down our range of operation, the region around 10pF was chosen for our objective of sub-picofarad capacitance measurement. The CIS was reconfigured by changing the various parameters in (1) to achieve the sensitivity of 8.1 mV/fF with Cdif f = 100 fF. In Table II the comparison with the state-of-the-art oscillator based capacitive sensor interfaces is presented. The sensitivity is higher than reported elsewhere, while comparable or better power and area numbers are obtained, for comparable technology nodes. V. C ONCLUSION The paper describes a capacitance to voltage conversion technique in a capacitance interface system implemented in a 0.13µm standard CMOS technology. A sensitivity of

Fig. 10. Measured output of the system for varying capacitance values. The highlighted range shows the system optimized for sub-picofarad capacitance measurement with higher sensitivity S = 8.1 mV/fF.

[1] J.C. Lotters and et.al., “A sensitive differential capacitance to voltage converter for sensor applications,” IEEE Transactions on Instrumentation and Measurement, vol. 48, no. 1, Feb 1999. [2] N. Madhu Mohan and et.al., “Digital converter for differential capacitive sensors,” IEEE Transactions on Instrumentation and Measurement, vol. 57, no. 11, Nov 2008. [3] G.S. Javed and G. Banerjee, “Integrated Temperature Sensor for Reconfigurable Radio Frequency Synthesizer,” in Proceedings of IEEE CONECCT 2015, Jul 2015. [4] F. Aezinia and B. Bahreyni, “An interface circuit with wide dynamic range for differential capacitive sensing applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 11, 2013. [5] A. Heidary and et.al., “Features and Design Constraints for an optimized SC Front-End Circuit for Capacitive Sensors with a wide dynamic range,” IEEE Journal of Solid-State Circuits, vol. 43, no. 7, 2008. [6] W. Bracke and et.al., “Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 1, 2007. [7] M. Machnoor and et.al., “Novel spike-based architecture for RFID and Sensor Communication System,” in Proceedings of 41st Annual Conference of IEEE Industrial Electronics Society, Nov 2015. [8] Hua Wang and et.al., “Phase noise and fundamental sensitivity of oscillator-based reactance sensors,” IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 5, May 2013. [9] G.S. Javed and et.al., “Differential Multi-phase DLL for Reconfigurable Radio Frequency Synthesizer,” in Proceedings of IEEE CONECCT 2014, Jan 2014. [10] Dong-Yong Shin and et.al., “A delta–sigma interface circuit for capacitive sensors with an automatically calibrated zero point,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 2, 2011. [11] Zhen Ye and et.al., “High-Performance Closed-Loop Interface Circuit for High-Q Capacitive Microaccelerometers,” IEEE Sensors Journal, vol. 13, no. 5, 2013. [12] Sheng-Yu Peng and et.al., “A charge-based low-power high-SNR capacitive sensing interface circuit,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, 2008.