DECEMBER 1993
WRL Research Report 93/8
A 300MHz 115W 32b Bipolar ECL Microprocessor Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, Leon Yang, John Fitch, William Hamburgen, Russell Kao, and Richard Swan
digi tal
Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA
The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There two other research laboratories located in Palo Alto, the Network Systems Laboratory (NSL) and the Systems Research Center (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge, Massachusetts (CRL). Our research is directed towards mainstream high-performance computer systems. Our prototypes are intended to foreshadow the future computing environments used by many Digital customers. The long-term goal of WRL is to aid and accelerate the development of high-performance uni- and multi-processors. The research projects within WRL will address various aspects of high-performance computing. We believe that significant advances in computer systems do not come from any single technological advance. Technologies, both hardware and software, do not all advance at the same pace. System design is the art of composing systems which use each level of technology in an appropriate balance. A major advance in overall system performance will require reexamination of all aspects of the system. We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of higher performance systems. Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals. We publish the results of our work in a variety of journals, conferences, research reports, and technical notes. This document is a research report. Research reports are normally accounts of completed research and may include material from earlier technical notes. We use technical notes for rapid distribution of technical material; usually this represents research in progress. Research reports and technical notes may be ordered from us. You may mail your order to: Technical Report Distribution DEC Western Research Laboratory, WRL-2 250 University Avenue Palo Alto, California 94301 USA Reports and notes may also be ordered by electronic mail. Use one of the following addresses: Digital E-net:
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A 300MHz 115W 32b Bipolar ECL Microprocessor Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, Leon Yang, John Fitch, William Hamburgen, Russell Kao, and Richard Swan
December, 1993
Abstract A full-custom single-chip bipolar ECL RISC microprocessor was implemented in a 1.0µm single-poly bipolar technology. This research prototype contains a CPU and on-chip 2KB instruction and 2KB data caches. Worst-case power dissipation with a nominal -5.2V supply is 115W. The chip has been designed for a worst-case clock frequency of 275MHz at a nominal supply. The chip verifies a new style of CAD tools developed during the design process, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques.
This Research Report is a reprint of a paper appearing in the November 1993 issue of the IEEE Journal of Solid-State Circuits.
digi tal
Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA
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Table of Contents 1. Introduction 2. Chip Overview 3. Bipolar Process Technology 4. Circuit Technology 4.1. Noise Margins 4.2. Clock Distribution 4.3. RAM Cell 4.4. Biases 4.5. Testing 5. CAD 5.1. Design Capture 5.2. Simulation 5.3. Generation of Layout 5.4. Design Verification 5.5. CAD Summary 6. Packaging 7. Summary Acknowledgements References
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List of Figures Figure 1: Die before gold metalization with floorplan Figure 2: CPU pipeline and machine organization Figure 3: Cross section of gold bus bars Figure 4: Die with gold bus bars Figure 5: Cascode multiplexor circuit Figure 6: Breakdown of single-ended noise margin Figure 7: Clock distribution network Figure 8: Cache RAM cell Figure 9: CPU operating frequency vs. supply voltage Figure 10: Typical cell schematic Figure 11: Flip-flop with built-in 4-input multiplexor Figure 12: Gate generated with silicide routing Figure 13: CBE transistor configuration Figure 14: Gate with silicide and metal routing Figure 15: IR drops on Vee Figure 16: IR drops on Vcs Figure 17: Package with thermosiphon Figure 18: Exploded view of package assembly Figure 19: Numerical model of die temperature Figure 20: Infrared photograph of operating chip
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List of Tables Table 1: Device counts, power, and area of each functional unit Table 2: Transistor parameters Table 3: Metal parameters
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1. Introduction Bipolar ECL technology has historically been used to implement high speed communication circuits and mainframe computers built with gate arrays and multichip modules. These gate arrays have had low integration compared with full-custom CMOS microprocessors. In addition, multichip modules typically have a power dissipation limit of under 30 Watts per chip. This further limits both the integration and circuit speed available. Moreover, a gate array design style pays a significant penalty in terms of the number of gates in series required to implement a particular function because of the limited gate selection (typically under 100, including power options) available in a gate array macro library, in contrast to the billions of gate circuit functions available in a custom ECL technology. The combination of all of these factors makes it difficult for ECL multichip gate array machines to compete with full-custom CMOS microprocessors. A full-custom design approach applied to ECL can provide logic density similar to full-custom CMOS. Full-custom ECL also provides added circuit speed by tailoring logic swings for specific circuits and allowing a wider range of circuit topologies. A full-custom ECL CPU and its caches can be integrated on a single die, and yields significantly higher performance. Although this die dissipates considerable power, it is only a single die, not a collection of many medium-power die as in a multichip CPU. A single high-power die can be cooled with a thermosiphon. This paper describes a full-custom single-chip ECL RISC microprocessor [5] which has been implemented in a 1.0µm single-poly bipolar technology. The chip contains a CPU and on-chip instruction and data caches. The 15.4 x 12.6 mm die contains 468K bipolar transistors and 206K resistors. Worst-case power dissipation with a nominal -5.2V supply is 115W. The chip has been designed for a worst-case clock frequency of 275MHz at a nominal supply. It has 202 ECL 100K inputs, 157 ECL 100K outputs, and 254 power pads, and is packaged in a 504 pin plastic pin grid array. A subset of the MIPS R6000 architecture is implemented. No floating-point, memory management, or integer multiplication and division support is provided on-chip. The chip is a research prototype designed to verify a new style of CAD tools, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques. The chip was designed largely with CAD tools developed by members of the design team. The schematics are graphical representations of C++ programs. The layout consists of 554 different cells, of which 93 are hand-drawn. The remainder are automatically synthesized leaf cells or composite cells placed by program and routed automatically. Over half of the point-to-point connections within a typical synthesized leaf cell are made with
