8-BIT PARALLEL ADDER-SUBTRACTOR

Advanced Computer Architecture

ST. XAVIER'S COLLEGE
Maitighar, Kathmandu



ADVANCED COMPUTER ARCHITECTURE
LAB ASSIGNMENT #2
Submitted by:
Surya Khanal
3rd Sem
46
Submitted to:


Signature
Remarks
Er. Anil Sah
Lecturer, Department of Computer Science


Er. Sanjay Kumar Yadav
Lecturer, Department of Computer Science


TITLE: VERIFICATION OF 8-BIT PARALLEL ADDER-SUBTRACTOR


THEORY:
A binary parallel adder is a digital function that produces arithmetic sum of two binary numbers in parallel. It consists of full-adder combinational arrangement thus, the output carry from one full adder connected to the input carry of next full- adder. In 8 bit binary parallel adder-subtractor there are 8 full adder connected in a parallel way. In this circiut the addition and subtraction is done through the same circuit.

The circuit for subtracting A - B consists of an adder with inverters placed between each data input B and the corresponding input of placed between each data input B and the corresponding input of the full adder. The input carry C0 must be equal to 1 when subtraction is preformed. The operation thus performed becomes A, plus the 1's complement of B, plus 1. This is equal to A plus 2's complement of B.

For unsigned numbers, that gives A - B if A >= B or the 2's For unsigned numbers, that gives A - B if A >= B or the 2's complement of (B – A) if A < B. complement of (B – A) if A < B. For signed numbers, the result is A - B, provided that there is no For signed numbers, the result is A - B, provided that there is no Overflow. Binary numbers in the signed-complement system are added Binary numbers in the signed-complement system are added and subtracted by the same basic addition and subtraction rules and subtracted by the same basic addition and subtraction rules as are unsigned numbers. as are unsigned numbers. Therefore, computers need only one common hardware circuit to Therefore, computers need only one common hardware circuit to handle both types of arithmetic. handle both types of arithmetic. In the figure 1.1 the full adder is shown:

















Fig 1.1 full adder



Table 1: Truth table for the full adder and subtractor

Inputs
Full Adder
Full Subtractor
A
B
C
Sum
Carry
Diff.
Borrow
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1










LOGIC DIAGRAM:
M


































Fig 1.2 (8 bit parallel adder-subtractor)
OBSERVATION:

After making the circuit diagram of the 8 bit parallel adder-subtractor following observation was done. When the value of 'M' in the cicuit remains 0, it works as the 8 bit parallel adder and when its value is changed to 1, it works as the 8 bit parallel subtractor. For the observation various 8 bits inputs A & B were given to the circuit and their respective outputs are listed below in the tables.


For addition:

Input
Output
C in
M
A
B
Sum
Carry out
0
0
00000001
00000001
00000010
0
0
0
00001011
00000111
00010010
0
0
0
10111011
01110111
00110010
1
0
0
11111111
11111111
11111110
1
0
0
01111111
01111111
11111110
0
0
0
01111110
01111110
11111100
0


For Subtraction:

Input
Output
C in
M
A
B
Difference
Carry out
1
1
00000011
00000011
00000000
1
1
1
11111111
00000000
11111111
1
1
1
10111010
11010101
01001101
0
1
1
11111111
11111111
00000000
1
1
1
00111001
11111101
10111010
0
1
1
01110000
10000011
10110010
0



CONCLUSION:
We prepared the circuit diagram for the 8 bit parallel adder-subtractor and observed the accuracy of the circuit by providing two 8 bits input to the adder and gained their output which all are true. Hence the parallel adder-subtractor shown in the figure 1.2 is verified.


REFERENCE:

https://www.scss.tcd.ie/john.waldron/cs1026/lec9adder.pdf
https://www.academia.edu/4020322/design_of_4-bit_adder_subtractor_composite_unit_using_2_s_complement_method



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