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Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates Khaled Ben Ali, César Roda Neve, Ali Gharsallah, Senior Member, IEEE, and Jean-Pierre Raskin, Senior Member, IEEE
Abstract—Substrate crosstalk into standard and trap-rich highresistivity silicon (HR-Si) substrates over a wide frequency range, from ultralow frequency (ULF) to extremely high-frequency band (EHF), is investigated using finite-element numerical simulations and experiments. It is demonstrated that low-frequency substrate crosstalk is strongly impacted by the presence of free carriers at the interface between the HR-Si substrate and the interconnection passivation layers. The efficiency of a trap-rich layer, a polysilicon layer thicker than 300 nm, placed at that interface to recover the nominal high-resistivity characteristic of the Si substrate is theoretically and experimentally demonstrated. Finally, the wideband crosstalk behavior of the HR-Si substrate with and without a trap-rich layer is modeled by means of a simple equivalent lumped-element circuit. The proposed model shows excellent agreement with finite-element numerical simulations and experimental data for frequencies above 100 kHz. Due to the introduction of a trap-rich layer, HR-Si substrate behaves as a lossless dielectric substrate. In that case, a purely capacitive electrical equivalent circuit is sufficient to properly describe the substrate crosstalk characteristics. Index Terms—Crosstalk, electrical equivalent circuit, finiteelement numerical simulation, high-resistivity Si substrate, oxide fixed charges, traps, ultrawideband (UWB) measurements.
I. I NTRODUCTION
C
ONTINUED downscaling of CMOS technologies has made the cointegration of high-speed digital circuits with high-performance RF analog devices and RF MEMS on the same substrate [1]–[3] possible. In such complex system-onchip (SoC) applications, the coupling of switching noise from digital circuits and MEMS devices into sensitive RF analog circuit blocks through the common silicon substrate is a major concern. Unlike microwave circuits on low-loss substrates Manuscript received June 21, 2011; revised August 18, 2011; accepted September 14, 2011. Date of publication October 27,2011; date of current version November 23, 2011. This work was supported in part by the Université catholique de Louvain, Louvain-la-Neuve, Belgium and in part by SOITEC, Grenoble, France. The review of this paper was arranged by Editor H. S. Momose. K. Ben Ali is with the Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain, 1348 Louvain-la-Neuve, Belgium, and also with the Research Unit of Microwaves Electronic Circuits and Systems, Faculty of Science of Tunis, Université de Tunis El Manar, 2092 Tunis, Tunisia (e-mail:
[email protected]). C. Roda Neve and J.-P. Raskin are with the Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain, 1348 Louvain-la-Neuve, Belgium. A. Gharsallah is with the Research Unit of Microwaves Electronic Circuits and Systems, Faculty of Science of Tunis, Université de Tunis El Manar, 2092 Tunis, Tunisia. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2170074
such as alumina and GaAs, the lossy nature of low-resistivity silicon substrate used in standard CMOS technology can have a significant impact on the performance of large and complex SoC. Indeed, the noise generated by the digital circuitry can be easily injected into and propagate through the silicon substrate and thus degrades the performance of the sensitive analog and RF integrated circuits (ICs) or even cause failure of the system. High-performance SoC applications impose stringent requirement on the substrate characteristics. An ideal substrate should be a good thermal conductor and provide good isolation for digital switching noise (preferably < −100 dB). Among the numerous wireless standards, ultrawideband (UWB) systems face many design and technological challenges since they operate at high frequencies and over a wide frequency band (3.1–10.6 GHz). Such systems are more sensitive to substrate noise that mostly originates from the synchronization clock (3, 10, 26, 100 MHz, etc.) and the high-speed digital circuits. Switching noise of such digital circuits propagates through the substrate and affects the different parts of the wideband system such as low noise amplifier [4], UWB RF filters [5], and voltage-controlled oscillator [6]. Among the many applications enabled by SoC, building blocks are reconfigurable RF systems that benefit from cointegration of RF MEMS devices with CMOS ICs. Although they offer high performance in a modular fashion, they still suffer from substrate coupling and crosstalk effect [7]. The use of a high-resistivity silicon (HR-Si) substrate has been proposed as an attractive material for cointegration of RF and mixed-mode signal systems [8]. It exhibits excellent RF properties with effective resistivity values of at least 3 kΩ · cm [9], and it is now widely available for industrial scale production. HR-Si substrate is fully compatible with silicon-on-insulator (SOI) technologies, and high-resistivity SOI (HR-SOI) wafer is nowadays presented as a mature and low-cost technology for high-performance mixed-mode integrated systems. However, the main challenge in using HR-SOI, or as soon as an oxide layer is deposited or grown on top of an HR-Si substrate, is to conserve the high-resistivity characteristics of the substrate. Indeed, the fixed oxide charges Qox at the SiO2 /Si interface attract free mobile carriers at the top surface of Si, creating a highly conductive layer underneath the oxide, which degrades the effective resistivity of the substrate. The reduction of the substrate effective resistivity will translate to an increase in the coplanar waveguide (CPW) transmission-line RF losses and an increase in the parasitic coupling (crosstalk) between devices and ICs lying on the same Si substrate [10]. Fortunately, such parasitic surface conduction (PSC) effect can
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BEN ALI et al.: CROSSTALK INTO STANDARD AND TRAP-RICH HR-Si SUBSTRATES
be effectively overcome by introducing a high density of traps near the insulating oxide. The traps capture the free carriers, thereby enabling the substrate to recover its nominal resistivity value and stabilizing the whole wafer surface. Several techniques can be used to introduce a trap-rich layer at the SiO2 /Si interface, such as ion implantation [11] and the deposition of a layer of amorphous silicon (a-Si) [12] or polycrystalline silicon (PSi) [13] between the HR-Si handle substrate and the oxide layer. We invite you to read the comparison between the different passivation techniques given by Chen et al. in [14]. To assess the substrate losses and coupling mechanisms and how technological solutions can improve the performance of RF, mixed-mode applications, and SoC, an accurate model of the substrate coupling, or crosstalk, mechanism becomes fundamental. Such model must be based on physical understanding of current flow paths in the silicon substrate. It should also cover the widest possible frequency range in order to provide a useful tool for the diversity of applications that can be found in current and future SoCs, from analog to digital, including MEMS and optoelectronic devices. Although the crosstalk dependence on substrate resistivity and separation between devices were presented by Raskin et al. in [15], neither the crosstalk behavior below 100 MHz nor the impact of PSC and its reduction by the introduction of a trap-rich layer were studied. In addition, the introduction of a trap-rich layer provides better isolation than guard ring [15] or metal Faraday cages [16]. In this paper, we investigate over a wide frequency range, from 100 kHz to tens of gigahertz, the substrate crosstalk in Si-based substrates, with focus on HR-Si substrates showing the PSC effect and its reduction using a trap-rich layer. To this purpose, we use finite-element numerical 2-D-simulations from Atlas SILVACO and measurements done on crosstalk test structures fabricated on different Si substrates. In Section II, we show the dependence of crosstalk on the Si resistivity and on the distance separating the noisy aggressor and the victim. Simulations and measurements to assess the impact of PSC on substrate crosstalk and its reduction using a high trap-rich PSi layer are presented in Section III. In addition, finally, an equivalent lumped-element electrical circuit, valid for frequencies starting from 100 kHz, is proposed in Section IV before concluding in Section V. II. S UBSTRATE C OUPLING IN Si AND SOI-L IKE S UBSTRATES The experimental crosstalk test structure consists of two identical metallic taps embedded in a coplanar structure for RF probe measurements, which represent the noisy aggressor and the victim, as shown in inset in Fig. 1. The 1-μmthick aluminum (Al) crosstalk test structure lies on a substrate composed of a 145-nm-thick oxide, a 750-μm-thick silicon substrate of various resistivity values, and a 0.5-μm-thick Al back metallization. The rectangular metallic pad size is of 50 μm × 150 μm, and they are spaced by 50 μm. Small-signal power transfer between both pads (S21 scattering parameter) is measured on-wafer from 100 kHz up to 4 GHz using a Rohde & Schwarz ZVR vector network analyzer that presents an extremely low-noise floor level, i.e., lower than −130 dBm.
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Fig. 1. Measured S21 parameters on standard (20 Ω · cm) and HR (5 kΩ · cm) silicon and quartz substrates. In the case of the Si substrates, the metallic pads and CPW feed lines are isolated from the substrate with a 145-nm-thick SiO2 layer. The gray area extending from 100 kHz until 100 MHz highlights the frequency band that was not experimentally studied in [15].
A. Influence of Silicon Substrate Resistivity As described in [15], the use of SOI in combination with HR-Si (ρ > 1 kΩ · cm) considerably reduces substrate crosstalk below 10 GHz, as compared to standard SOI (ρ = 20 Ω · cm). The measured crosstalk characteristic presented in Fig. 1 for a standard resistivity Si substrate of ρ = 20 Ω · cm perfectly corresponds to the analysis proposed in [15]. It presents two inflection points noted f1 and f2 , a 40-dB/dec slope at low frequencies (below f1 ) related to the 145-nm oxide, and a slope of 20 dB/dec at high frequencies (above f2 ) illustrating the capacitive coupling. However, measurements performed on HR-Si substrate below 10 MHz indicate that the S21 coupling parameter does not present a slope of 40 dB/dec, as theoretically predicted in [12] and [15], but a slope of about 20 dB/dec. In order to understand this abnormal or at least unpredicted behavior at low frequencies, the crosstalk for an HR-Si substrate of ρ = 5 kΩ · cm has been simulated with Atlas numerical software. As predicted by the lumped equivalent circuit proposed in [15], simulations show a 40-dB/dec slope below f1 in the case of HR-Si substrate. However, when fixed charges Qox at the oxide–substrate interface are introduced and thus the PSC effect is considered, the low-frequency slope of S21 is indeed close to 20 dB/dec, as shown in Fig. 2. This behavior cannot be modeled by the equivalent electrical circuit proposed in [15], as it will be discussed in Section IV. B. Influence of the Distance Between the Noisy Aggressor and the Victim Crosstalk structures composed of two metallic pads spaced by different distances d have been measured, and the results are presented in Fig. 3. At a frequency of 10 MHz, the crosstalk decreases from −60 to −70 dB when spacing distance d increases from 50 to 150 μm. We observe dependence of the crosstalk on spacing, as described in [15], i.e., increasing the distance between the sensitive and noisy devices shifts the crosstalk characteristic downward. Similar to Fig. 2, the S21
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Fig. 2. Simulated crosstalk into the HR-Si substrate with and without fixed charges Qox .
Fig. 3. Measured crosstalk on the HR-Si substrate as a function of the distance between the two metallic pads.
parameter presents a slope of 20 dB/dec below f1 . However, it is worth noting that the crosstalk level is unchanged for the three values of d for frequencies lower than 300 kHz. This can be linked to the PSC effect and, more exactly, to the presence of the inversion layer underneath the oxide layer. The independence of the substrate coupling with the distance has been also observed over a wide frequency band from 10 MHz to 10 GHz in the case of heavily doped buried layer bulk CMOS technology in [17]. Noise at low frequencies can have an impact on victims far away from the aggressor. This could be an important drawback for SoC where low-power digital circuits and MEMS actuators [7] operating at low frequencies, tens and hundreds of kilohertz, share the same substrate than high-speed memory devices, wireless, and power handling circuit. Due to the substrate crosstalk at low frequencies, some systems could not be integrated into the same chip, but should have to be fabricated on a different substrate or chip, which corresponds to a system-in-package (SiP) approach, and with, consequently, an increase in the cost per system. C. Impact of PSC Effect Oxidized HR-Si substrate is known to suffer from PSC and resistivity degradation near the insulating oxide. Indeed,
Fig. 4. Simulated resistivity versus substrate depth for p-type 5-kΩ · cm HR-Si substrates with and without a trap-rich layer. Qox = 1011 /cm2 and Dit = 1011 /cm2 .
the existence of fixed oxide charges Qox within the SiO2 /Si interface creates a nonhomogenous surface conduction layer all over the wafer by attracting free carriers at the HR-Si surface, hence creating an inversion/accumulation zone, reducing the effective resistivity, and increasing RF losses and substrate crosstalk. Fig. 2 highlights the enormous impact of the PSC effect on substrate crosstalk behavior. Indeed, a value as low as Qox = 1011 cm−2 degrades the S21 scattering parameter by more than 30 dB at 10 MHz. This simulation result is in good agreement with the measurement results presented in Fig. 1. To get more physical insights about the impact of PSC on the effective resistivity of the silicon substrate, numerical simulations have been run to extract the resistivity profile along the semiconductor depth, as shown in Fig. 4. Because of the metal–semiconductor work-function difference and the fixed oxide charges, the inversion layer right underneath the oxide drastically decreases the resistivity of the substrate over a depth of approximately 3 μm. Such parasitic conduction effect can be efficiently reduced by introducing a high density of traps near the insulating oxide, as detailed in next section. III. S UBSTRATE T ECHNOLOGY FOR C ROSSTALK R EDUCTION The highly conductive thin layer (PSC) at the SiO2 /Si interface that originates from the positive fixed charges inside the oxide layer or biasing of the interconnection lines strongly degrades the substrate crosstalk characteristics over a wide frequency band. This issue can be overcome by introducing a trap-rich layer between the oxide and the HR-Si substrate, which captures the free carriers and locally depletes the HR-Si substrate [18]. A. Introduction of a Trap-Rich Layer at the SiO2 /Si Interface The presence of a high density of traps is modeled in two different ways. The first approach considers the introduction of a high-enough density of traps Dit at the SiO2 /Si interface to overcome the PSC effect. The second approach consists in
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Fig. 5. Simulated HR-Si substrate without and with Qox and in the presence of a trap-rich PSi layer of 300-nm thick.
placing a thin PSi layer of 300-nm thick just underneath the SiO2 layer. The high density of grain boundaries in the PSi layer provides a large number of surface and volumetric traps. To favor the trap mechanism, the defects’ distribution in the Si bandgap was mainly considered to be a tail distribution rather than a Gaussian distribution. The simulated resistivity profile below one of the metallic pads of the crosstalk structure, biased at zero dc voltage, is shown in Fig. 4. We observe that, in both cases, the high resistivity value is recovered at the top surface of the substrate, and a buried depletion region is created before reaching the nominal resistivity of the HR-Si substrate, i.e., 5 kΩ · cm for the simulated case, at a depth larger than 10 μm. Fig. 5 shows the simulated crosstalk response between both metallic pads for an oxidized HR-Si with and without the introduction of a 300-nm-thick PSi layer, acting as a traprich layer, at the SiO2 /Si substrate interface. These results clearly show the efficiency of the PSi layer in minimizing the noise coupling. We observe a reduction of more than 20 and 35 dB at 100 kHz and 10 MHz, respectively. Basically, due to the PSi layer, the intrinsic high-resistivity properties of the HR-Si are recovered, i.e., the impact of Qox , and thus, PSC is cancelled out. This tremendous improvement is also experimentally demonstrated in Fig. 6 with the introduction of a 300-nm-thick undoped PSi layer. The trap-rich HR-Si substrate behaves as a lossless substrate (purely capacitive coupling) over nearly the whole measurement frequency range. Indeed, the S21 parameter shows a 20-dB/dec dependence value over the whole frequency band above 1 MHz, similar to the quartz substrate. It is worth noting that the 40-dB/dec slope of the S21 parameter below f1 , theoretically predicted in [15], is recovered for the HR-Si substrate (see Figs. 2 and 5) due to the introduction of a trap-rich layer underneath the oxide. B. PSi Layer Thickness To provide a high density of traps between the Si substrate and the oxide, we deposited a layer of PSi by means of lowpressure chemical vapor deposition at 625 ◦ C. The resulting wafer followed wet thermal oxidation to obtain the desired thickness of SiO2 on top of the final 300-nm-thick layer of PSi exhibiting a typical columnar grain microstructure [9].
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Fig. 6. Measured S21 response on quartz and HR-Si substrates with and without the 300-nm-thick PSi layer.
Fig. 7. Dependence of crosstalk on the PSi layer thickness for an HR-Si substrate.
The numerous traps created by silicon dangling bonds in PSi are able to absorb the free carriers attracted at the SiO2 /Si interface and greatly reduce substrate losses. Fig. 7 displays the crosstalk response between both metallic pads for deposited PSi layers ranging from 76 up to 435 nm. The direct relationship between the crosstalk reduction and the PSi thickness is clearly observed. A thickness of 435 nm is needed to approach the crosstalk behavior of a lossless Si substrate. The critical thickness to get rid of the PSC effect will depend on the PSi grain size, as experimentally demonstrated in [9]. A PSi layer characterized by small grains such as crystallized a-Si [9] provides an efficient trap-rich layer already for a thickness of 280 nm. IV. C ROSSTALK M ODELING With a high level of integration in SoC applications, it is mandatory to incorporate substrate coupling into the compact models in order to properly simulate the wideband electrical behavior of ICs. Moreover, the development of a lumpedelement equivalent circuit for substrate crosstalk provides a precious tool to understand deeper the physical coupling mechanisms and to predict the efficiency of various crosstalk reduction techniques. A new lumped-element equivalent circuit is
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derived from [15] are given by −1 σSi · Apad R 2 = K2 · tSi C2 = K2 · ⎡
ε0 · εSi · Apad tSi
R3 = ⎣K3 ·
C3 = K3 ·
Fig. 8. Lumped-element electrical equivalent circuit for substrate crosstalk modeling considering the presence the PSC effect Rinv and trap-rich layer Cit . The values introduced in the PSC lumped model are C1 = 1.4 pF, Cd = 80 fF, Rinv = 0.09 MΩ, R3 = 0.6 MΩ, C3 = 9.6 fF, R2 = 5 MΩ, and C2 = 1.04 fF; for the PSi lumped model, the values are C1 = 1.4 pF, Cd = 4 fF, Cit = 18 fF, Rinv = 17 MΩ, R3 = 0.6 MΩ, C3 = 30 fF, R2 = 5 MΩ, and C2 = 1.04 fF.
proposed hereafter to describe the PSC effect and its reduction by the introduction of a trap-rich PSi layer. Simulations using this model over a wide frequency band are compared with measurements to validate the approach.
4 · ln
The lumped-element equivalent circuit modeling the coupling between two metallic pads of same size lying on an oxidized HR-Si substrate, including the PSC effect, is shown in Fig. 8. Similar to the model presented in [15], capacitance values noted C1 represent the coupling between the metallic pads and the SiO2 /Si substrate interface, i.e., R2 and C2 , which are the resistive and capacitive couplings between each pad and the wafer backside metallization, and R3 and C3 , which are the resistive and capacitive coupling paths between both metallic pads through the silicon substrate. The analytical expressions of those lumped elements are given hereafter C1 = K1 ·
ε0 · εox · Apad tox
(1)
where ε0 , εox , tox , and Apad are the absolute permittivity (vacuum), oxide relative permittivity, the thickness of the oxide layer, and the area of the metallic pad, respectively, and K1 is a fringing factor accounting for the fringing field effects. For identical pads with an area of Apad = W × W and spacing distance d, the expressions of R3 , C3 , R2 , and C2
π · σSi π·(d−W ) W +t
(3) ⎤−1 · W⎦ +1
π · ε0 · (εSi + 1) ·W ) 4 · ln π·(d−W W +t + 1
(4)
(5)
where εSi , σSi , and tSi are the relative permittivity, the conductivity, and the thickness of the silicon substrate, respectively, t is the thickness of the conductor (Al metallic pad), and K2 and K3 are the fringing factor coefficients, and their expressions are given in [15]. In order to introduce the impact of PSC, the formed highly conductive layer is modeled by the resistance Rinv [see (6)] underneath which there is a depletion region that can be described by its depletion capacitance Cd [see (7)], where Xd,max is the maximum depletion depth expressed by (8). ρinv , tinv , d, NA , ni , and K are the resistivity and thickness of the inversion layer, the spacing distance between each metallic pad, the acceptor concentration, the intrinsic carrier density, and a fringing factor, respectively. The three aforementioned equations are as follows: ρinv · d W × tinv ε0 · εSi Cd = K · · Apad Xd,max
4 · ε0 · εSi · ln( NnAi ) Xd,max = . q 2 · NA Rinv = K ·
A. Equivalent Circuit Including the PSC Effect
(2)
(6) (7)
(8)
The simulated results based on the equivalent circuit in Fig. 8 show quite good agreement with the measured data over the entire frequency band (see Fig. 9). Due to the introduction of the lumped elements, i.e., Rinv and Cd , the PSC effect at the SiO2 /Si interface is well described, and thus, a typical 20-dB/dec slope is simulated at low frequency for an HR-Si substrate, in agreement with the measurements, contrary to the 40-dB/dec slope predicted in [15]. The calculated lumped elements take into account the distance d between the two metallic pads, and thus, the impact of the distance between the aggressor and the victim is properly modeled. However, it is worth to notice that, for d larger than a few hundreds of micrometers, distributed effects into the substrate might impact the crosstalk behavior over the frequency range. In that case, several lumped-element equivalent circuits must be cascaded to model the propagation of the coupling signal into the substrate. Atlas numerical software takes into account those distributed effects along the coupling path in the Si substrate.
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V. C ONCLUSION
Fig. 9. Measured and modeled crosstalk in HR-Si substrate without and with the 300-nm-thick PSi layer.
The substrate crosstalk on Si (and HR-Si) substrates over a wide frequency band has been analyzed. A lumped-element equivalent circuit model from 100 kHz up to several gigahertz, based on the physical understanding of substrate crosstalk, has been proposed and compared with measurements and numerical simulations. It includes the impact of the PSC effect and its reduction due to the introduction of a trap-rich layer at the oxide-Si substrate interface. It has been proven that the discrepancy between measurements and previous crosstalk models [15], for Si and HR-Si substrates at low frequencies, is due to the presence of a highly conductive layer (PSC) at the Si surface. The introduction of a trap-rich layer of PSi has been successfully simulated and compared with crosstalk measurements. It has been proven to be an efficient solution to drastically reduce the crosstalk at frequencies below 10 GHz to fully leverage the excellent properties of the HR-Si (or HR-SOI) for low-loss RF, mixed-mode, and SoC applications. Due to this trap-rich PSi layer, a purely capacitive lumped equivalent circuit properly describes the quasi-lossless HR-Si substrate. This simple capacitive model can be used by RF designers to build RF, analog, and digital devices lying on a PSi trap-rich HR-Si substrate.
ACKNOWLEDGMENT The authors would like to thank Dr. D. Lederer from the Université catholique de Louvain, as well as Dr. E. Desbonnets and Dr. F. Allibert from SOITEC for their helpful discussions. Fig. 10. Purely capacitive crosstalk model for the trap-rich HR-Si substrate. The values introduced in the capacitive lumped model are C1 = 1.4 pF, Cd = 4 fF, Cit = 18 fF, C3 = 30 fF, and C2 = 1.04 fF.
B. Equivalent Circuit Including a Trap-Rich Layer The introduction of a trap-rich layer below the oxide has a double effect on the crosstalk equivalent circuit: 1) the increase in the Rinv value because of the drastic carrier mobility reduction caused by the trapping mechanisms and 2) the presence of parallel capacitance Cit with Cd , whose value depends on the trap density of the PSi layer. Considering a large value for Rinv and Cit in the equivalent circuit in Fig. 8 (the fitting values are given in the caption of Fig. 8), a typical 20-dB/decslope crosstalk characteristic can be obtained over the whole frequency band that is in agreement with the measurements. Again, this simple lumped-element model demonstrates that minimum crosstalk coupling can be reached over a wide frequency band by the introduction of a trap-rich layer in the case of HR-Si substrate. This is in agreement with the Atlas simulations presented in Section III and Fig. 4. Finally, due to the introduction of a trap-rich layer, the crosstalk behavior of an HR-Si substrate can be modeled by a simple capacitive model, as presented in Fig. 10. This purely capacitive model fits very well with measurements in Fig. 9 for frequencies higher than 1 MHz.
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[10] B. Rong, J. N. Burghartz, L. K. Nanver, B. Rejaei, and M. Van der Zwan, “Surface-passivated high resistivity silicon substrates for RFICs,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 176–178, Apr. 2004. [11] Y. H. Wu, A. Chin, K. H. Shih, C. C. Wu, C. P. Liao, S. C. Pai, and C. C. Chi, “RF loss and crosstalk on extremely high resistivity (10 k– 1 MΩ · cm) Si fabricated by ion implantation,” in Proc. IEEE MTT-S Dig., 2000, pp. 221–224. [12] H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, “Low-loss CPW on surface stabilized high-resistivity silicon,” IEEE Microw. Guided Wave Lett., vol. 9, no. 10, pp. 395–397, Oct. 1999. [13] D. Lederer and J.-P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate,” IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1664–1671, Jul. 2008. [14] C. Chen, R. Wang, Y. Su, and T. Hsueh, “A nanocrystalline silicon surfacepassivation layer on an HR-Si substrate for RFICs,” IEEE Electron Device Lett., vol. 32, no. 3, pp. 369–371, Mar. 2011. [15] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2252–2261, Dec. 1997. [16] S. Stefanou, J. S. Hamel, P. Baine, M. Bain, B. M. Armstrong, H. S. Gamble, M. Kraft, and H. A. Kemhadjian, “Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 486–491, Mar. 2004. [17] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1212–1219, Oct. 1994. [18] K. Ben Ali, C. Roda Neve, A. Gharsallah, and J.-P. Raskin, “Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates,” in Proc. 10th Top. Meeting Silicon Monolithic Integr. Circuits RF Syst.—SiRF, New Orleans, LA, Jan. 11–13, 2010, pp. 212–215.
Khaled Ben Ali was born in Sfax, Tunisia, in 1978. He received the M.S. degree in electronics from the Faculty of Sciences of Tunis, Tunis, Tunisia, in 2001 and the M.S. degree in instrumentation and industrial measurement from the National Institute of Applied Science and Technology, Tunis, in 2004. He is currently working toward the Ph.D. degree with the Microwave Laboratory, Université Catholique de Louvain, Louvain-la-Neuve, Belgium, and the Faculty of Sciences of Tunis. From 2004 to 2008, he was an Assistant Lecturer with the Higher Institute of Dramatic Arts and the Higher Institute of Medical Technologies of Tunis. His research interests include the characterization of high-resistivity Si substrates, losses and crosstalk of passive and active devices for RF applications and RF MEMS devices.
César Roda Neve was born in Madrid, Spain, in 1975. He received the Industrial Engineer Degree from the ICAI Universidad Pontificia de Comillas, Madrid, Spain, in 2000. He is currently working toward the Ph.D. degree with the Microwave Laboratory, Université Catholique de Louvain, Louvainla-Neuve, Belgium. From 2004 to 2006, he was a Teaching Assistant and a Researcher Engineer with the Department of Electronics, Charles III University of Madrid, Madrid. He worked on pulsed mode-locked lasers and laterally coupled diode lasers for ROF links and optoelectronic up/down conversion. His research interests include wideband on-wafer characterization of advanced passive and active devices in silicon metal–oxide–semiconductor technology, substrate crosstalk, silicon-on-insulator, high-resistivity substrates, on-wafer temperature characterization, transmission-line losses, and interconnects.
Ali Gharsallah (M’01–SM’08) received the B.S. degree in radio-frequency engineering from the Higher School of Telecommunication of Tunis, Tunis, Tunisia, in 1986 and the Ph.D. degree from the Engineering School of Tunis, Tunis, in 1994. Since 1991, he has been with the Department of Physics, Faculty of Sciences of Tunis, Tunis. He is currently a Full Professor of electrical engineering and Director of Engineering in the Higher Ministry Education of Tunisia. He is the author of about 55 papers published in scientific journals and 80 conference papers. He supervised more than 20 thesis and 50 Master’s thesis. His current research interests include smart antennas, array signal processing, multilayered structures, and microwave integrated circuits.
Jean-Pierre Raskin (M’97–SM’06) was born in Aye, Belgium, in 1971. He received the Industrial Engineer degree from the Institut Supérieur Industriel d’Arlon, Belgium, in 1993 and the M.S. and Ph.D. degrees in applied sciences from the Université Catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. From 1994 to 1997, he was a Research Engineer with the Microwave Laboratory, UCL. He worked on the modeling, characterization and fabrication of MMICs in silicon-on-insulator (SOI) technology for low-power low-voltage applications. In 1998, he joined the Deparment of EECS, University of Michigan, Ann Arbor. He has been involved in the development and characterization of micromachining fabrication techniques for microwave and millimeter-wave circuits and microelectromechanical transducers/amplifiers working in harsh environments. In 2000, he joined the Microwave Laboratory, UCL, as an Associate Professor. Since 2007, he has been a Full Professor and the Head of the Microwave Laboratory, UCL. From September 2009 to September 2010, he was a Visiting Professor with Newcastle University, Newcastle Upon Tyne, U.K. He is the author or coauthor of more than 350 scientific articles. His research interests include the modeling, wideband characterization, and fabrication of advanced SOI metal–oxide–semiconductor field-effect transistors as well as micro- and nanofabrication of MEMS/NEMS sensors and actuators, including the extraction of intrinsic material properties at nanometer scale. Dr. Raskin is a EuMA Associate Member and a member of the Research Center in Micro- and Nanoscopic Materials and Electronic Devices, UCL.
