SUPERCONDUCTING CIRCUITS DESIGN TOOL: APPLICATION TO HIGH FREQUENCY SIGMA DELTA ADC Rachid Guelaz, Patricia Desgreys and Patrick Loumeau
[email protected] LTCI-CNRS UMR 5141 - INSTITUT TELECOM – TELECOM PARISTECH - PARIS-FRANCE
Abstract We present an application tool dedicated to superconducting circuits design. Based on the use of VHDL-AMS language on System Vision software, we developed an innovating approach with top-down methodology to specify the RSFQ circuits. We take the example of a sigma-delta bandpass ADC and show the different processes used to design it. The demonstration shows the complete system in mixed signal language VHDL-AMS with the digital part in VHDL, the SNR can be followed block after block. Then, an example of parameter optimization in the modulator is performed.
A 2nd order sigma-delta bandpass ADC with a technology Nb/AlO/Nb for the Josephson junctions is developed. Operation point corresponds to clock frequency of 10GHz with temperature of 4°K. We perform a system analysis and a top-down design to achieve an implementation composed by Josephson junctions for each system part [4]. Fig. 1 shows the circuit used for the demonstration. cos(n.π/2) {-1 ;0 ;1} Real output
Lowpass decimation filter Bandpass Sigma-Delta modulator
Imaginary output
Lowpass decimation filter -sin(n.π/2) {0 ;-1 ;0 ;1}
1. Introduction
Superconducting circuit Clock Resonator
The RSFQ (Rapid Single Flux Quantum) logic is very low power consumption and ultra-fast electronic logic based on the benefits of superconductivity and is considered as the best alternative to CMOS in the ITRS roadmap for the highest frequency logic circuit operation (i.e. sub-THz or > 200 GHz circuit clock frequency). Specificity of this technology is in the use of Josephson junctions (three layers superconducting device) which could generate high frequency pulses train. Association of several junctions could product logic cells but combination of different logic cells could modify completely the predicted operation. Usual softwares as Pscan [1] or JSim [2] are limited because of the junction modeling that could not be extended or modified. Functional validation could be only obtained with several simulations and empirical approaches. Our design tool consists in the use of VHDL-AMS language to describe circuits with functional elements decomposition and their validations. Technological parameters (Nbn/Tax/Nbn [3] or Nb/AlO/Nb) are used to specify junction with integration of tolerance (technological dispersion) between junctions and noise is introduced by the mean of temperature value. For example, we study the case of a superconducting sigma delta bandpass modulator [4] operating at 10GHz. Performances in term of SNR (Signal Noise Ratio) are analyzed and optimized to obtain the better ADC resolution. Demonstration results show an innovative methodology to design RSFQ circuits taking into account technology specificities.
2. Design principle: application to the sigma delta bandpass ADC
Vin(t)+
Σ
H(z)
Clock
Comparator Rc
L1
L2
Ip
y[n]
-
Vc
JJ1
1-bit DAC
Comparator
C
Vin(t)
Figure 1: Sigma-Delta classic 2
L
IL
JJ2
Modulator Output
JJ3
nd
order architecture with its schematic RSFQ design
The modulator is composed by three elements: clock generation, comparator and resonator which have been simulated and validated separately in a first step. The heart of our tool is based on the modeling of the junction Josephson with the integration of technological parameters (critical current Ic, resistance Rn, capacitor Cs) and with a possible extension to noise and dispersion parameters. A stable clock frequency is obtained with the application of a DC voltage at node Vc. The resonator frequency is fixed at Fclock/4. In a classical operating mode, the comparator junctions are identical. Clock stage and comparator association is done by the inductor L2. The second step consists in clock value refinement and design of L2 in order to have the comparison result between two clock pulses. The post-treatment is operated with Scilab software for SNR calculation. Figure 2 illustrates the temporal evolution of the clock and the modulator output. Presence of a pulse is interpreted as a “1” logic level. Normalisation in binary interpretation is used to calculate SNR.
Variation applied on JJ2 60 50
S N R (d B )
40 30 20 10 0 -0,03
-0,025
-0,02
-0,015
-0,01
-0,005
0
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Critical current relative variation JJ2
Variation applied on JJ3 60 50
SN R (d B )
40 30 20 10 0 -0,03 -0,025
-0,02 -0,015
-0,01 -0,005
0
0,005
0,01
0,03
Critical cur re nt r e lative var iation JJ3
Figure 3: SNR_max obtained with physical dispersion applied on the comparator junctions Figure 2: Temporal evolution at top and output
spectral representation at bottom Noise Transfer Function is highlighted in this result with its particular form of rejected noise out of the interest bandwidth (2,459GHz – 2,541GHz). Signal is identified at the particular frequency of 2,51GHz. We simulate variation on inductance L2 in order obtain the best SNR. In theory, the circuit equations could not permit us to optimise the SNR results due to their complexity.
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When junction dispersions are over the variation of 2%, the simulation results show an unstable operating mode. This example of dispersion applied on physical characteristics shows the interest to this tool in RSFQ circuits design. Performance and operating mode could be obtained as the physical real case.
3. Conclusion The demonstration shows the capability of your RSFQ circuit methodology design to realize circuits based on topdown approaches and refinements with accordance to technology process.
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5. References
SN R (d B )
35 25 15 5 -0,5
-5 0
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L2 (pH)
Figure 3: SNR_max obtained with variation on L2 This example shows that the SNR is dependent on the comparator decision instant characterized by L25.25pH the sigma delta modulator becomes unstable. We observe that the SNR is high when the instant decision in low, and a quasi linear decrease on the SNR as function to L2. To obtain the best circuit performance, we localize the L2 value (0.5pH) for the best SNR (50dB) and we simulate relative dispersion of 2% on the critical current parameter Ic of each comparator junction JJ2 and JJ3. This method design could be used to identify critical element RSFQ cells and optimized it.
[1] S. Polonsky et al.: “PSCAN’96 : New software for siulation and optimisation of complex RSFQ Circuits”, Trans. On Applied Sperconductivity, Vol.7, No.2, June 1997. [2] E.S. Fang, T. van Duzer, “A josephson Integrated Circuit Simulator (JSIM) for superconductive Electronic Application”, 2nd ISEC, Tokoyo, Japan, pp. 407-410, 1989. [3] E. Baggetta, R. Setzu, J-C. Villégier, M. Maignan: “Implementation of basic NBN RSFQ Logic Gates of a wide-Band Sigma-Delta Modulator”, Applied Superconductivity Conference, Seatle. 2006. [4] R. Guelaz, P. Desgreys and P. Loumeau “A sigma-delta bandpass ADC modelling in superconducting RSFQ technology with VHDL-AMS,” Forum on Design and Languages FDL2008, Stuttgart, Germany, September 2008.
Acknowledgement This work is supported by ANR-Project: HyperSCANANR/06 TCOM 023.
