1
RF-pad, Transmission Lines and Balun Optimization for 60GHz 65nm CMOS Power Amplifier ∗ University
Sofiane Aloui∗ , Eric Kerherve∗ , Robert Plana† and Didier Belot‡ of Bordeaux, IMS Laboratory, 351 Cours de la Liberation, 33405 Talence Cedex, France Email: {sofiane.aloui, eric.kerherve}@ims-bordeaux.fr † LAAS-CNRS, 7 avenue du fonel Roche, 31077 - Toulouse Cedex 04 ‡ STMicroelectronics, Central R&D, 38926 Crolles Cedex
Abstract— Design and optimization of 65nm CMOS passive devices which are used in the implementation of a 60GHz Power Amplifier (PA) are presented. The targeted application is the low cost Wireless Personal Area Network (WPAN). A new optimized Radio Frequency (RF)-pad is used to minimize the losses of the PA access. The PA is matched via balun and Transmission Lines (T-Lines). T-Lines ensure both broadband inter-stage matching and biasing. S-parameters and large signal measurement results are demonstrated and compared with electromagnetic simulations. The PA achieves a maximum output power Psat of 7.3dBm with a gain of 8.5dB while consuming 96mA from a 1.2V supply. The active die area of the chip is 0.065mm2 . Additionally, innovative technique is adopted in the balun design to improve the balanced-to-unbalanced mode conversion and PA performances.
•
•
Section 2 presents the experimental results of a 65nm CMOS 60GHz fully integrated PA. Lumped and distributed passive elements are used. The PA reaches high gain and Psat . The PA performances are compared with PAs [2]-[3] designed with the same technology. Section 3 discusses about the balun design which is used as a Distributed Active Transformer (DAT) at the input and the output of the PA. Generally, three-port mixedmode S-parameters characterize the balun performances. In this paper, electromagnetic simulations are performed to visualize the electric and magnetic fields amount which are responsible for the voltage and current crossing over the balun. Finally, a high performance balun using an innovative methodology design is presented.
I. I NTRODUCTION
II. PASSIVE DEVICES
S
TANDARDS based on Bluetooth or WiFi have reached the maturity in terms of performances and marketplace. Moreover, they are not able to ensure gigabit wireless communication data rate. IEEE 802.15.3C standard occupies a free 7GHz unlicensed band around 60GHz to support faster and safer link [1]. This application targets a large scale market and a large volume production. Therefore, a cost constraint is imposed. In this context, a 65nm bulk CMOS technology (ρ = 20Ω.cm) is chosen to design the PA.
A. RF-Pad optimization
STMicroelectronics provides the 65nm CMOS technology with 7 metal layers and an Alucap layer. Low power transistors are the standard active devices. They offer a high unity current gain frequency (ft =160GHz) and a high maximum oscillation frequency (fmax =200GHz).
Here, an investigation is brought to determine the impact of the substrate in the RF-pad design. The bottom metals are suppressed and the RF-pad is exposed to the silicon substrate
Most of today’s pad realizations are composed by the top metals (Metal 6 or Metal 7 and Alucap) and by the bottom metals (Metal 1 and Metal 2) representing the solid metal shield. The main motivation of this design is the reduction of the substrate coupling and the improvement of the quality factor. This technique suffers from capacitive coupling losses because of the low thickness of the Back End Of Line (BEOL) in the emerging CMOS technology [4].
Substrate
The challenge in CMOS technology design is to take into account a maximum of high frequency considerations as metal and substrate losses, return current losses, tee and L junctions, access to transistor, pad capacitor. This work focuses on passive devices characterization and their optimization. This paper is organized in three sections.
60 Pad's capacitance (fF)
•
Substrate
Section 1 details the impact of RF-pad at millimeterwave (mmW) frequencies. Both traditional and optimized RF-pads are presented and measured. Electrical characteristics of Co-Planar Waveguide (CP W ) T-lines and tee junction are highlighted.
Simulation Non-shielded RF-pad Shielded RF-pad
50 40 30 20 10 0
20
40
60
80
100
freq, GHz
Fig. 1.
Measured and simulated capacitance of RF-pads
120
2 2.5
to support that characterization. Additionally, only Metal 7 and Alucap are used as a top plate to obtain the minimum capacitance. Fig. 1 depicts the two octagonal contact pads. The pad pitch is 100µm. The two pads are fabricated and measured from DC to 110GHz. The intrinsic capacitance (Cp ) of the shielded (Sh) RF-pad varies from 45f F to 40f F (11%). Whereas, the Cp of the non-shielded (N Sh) RF-pad varies from 30f F to 15f F (50%). Nevertheless, for frequencies beyond 55GHz the N Sh RF-pad presents almost the same Cp value and is equal to 16f F (cf. Fig. 1). This pad has a quasi-constant capacitance and can be used for the most important mmW applications which are centred at 60GHz, 77GHz and 94GHz.
Loss (dB/mm)
2.0
Measurement Simulation
1.5 1.0 0.5 0.0 0
20
40
60
80
Fig. 3.
Measured losses of a 50Ω CPW line 3
1
Investigating to lower Cp has an important effect in the design of PA, LNA or VCO. For instance, at 60GHz, the input and the output impedances are deviated from 50Ω to Z1pad = (42 − j ∗ 9)Ω for the N Sh RF-pad and is drastically deviated to Z2pad = (15 − j ∗ 13)Ω for the Sh RF-pad (cf. Fig. 2). In fact, the impedance deviated by the Sh RF-pad is closer to the input impedance of the transistor (around 10Ω) than the impedance deviated by the N Sh RF-pad. This behavior is advantageous for the matching in the design of single-function circuit. Nevertheless, the ultimate goal of mmW applications is to design fully integrated transceivers. Consequently, high-loss passive devices are required and must be added for each circuit to match every stage to 50Ω in the transceiver design. That drops the total gain of the transceiver. The insertion loss is shown in Fig. 2 to quantify the effect of the mismatching caused by the RF-pad. At 80GHz, when the input impedance Zin = 50Ω, the attenuation reaches 1.3dB for the Sh RF-pad and only 0.7dB for the N Sh RF-pad. If ∗ Zin = Zin (conjugate impedance), the N Sh RF-pad causes more attenuation (0.5dB vs. 0.3dB). This result is expected because of the substrate losses which increase more rapidly than the conductor losses at high frequencies.
S(ii)
For Zin = 50 Ohm @ 60GHz Z_1pad=41-j*12
Z_2pad=31-j*22 RF probe
50 Ohm
0.0
-0.5
-0.5
-1.0
-1.0
-1.5
-1.5
Non-shielded RF-pad Shielded RF-pad
-2.0
-2.0
-2.5 0
20
40
60
80
Freq, GHz
Fig. 2.
Insertion loss of the SH and N Sh RF-pads
100
-2.5 120
Loss (Zin=Z*) (dB)
Loss (Zin=50Ohm) (dB)
freq (1.000GHz to 110.0GHz) 0.0
100
freq, GHz
Fig. 4.
2
Tee junction turrent distribution and lumped model
B. CPW characterization The thin BEOL of CMOS technology makes hard a realization of high characteristic impedance (Zc ) line with microstrip line. Consequently, CPW line is chosen for our design. To obtain a Zc = 50Ω, the width (w) and the gap (g) separating the RF line and the adjacent ground plan are set to (w, g) = (10µm, 6.5µm). The CPW T-Line exhibits an attenuation of 1.6dB/mm at 60GHz (cf. Fig. 3). C. Tee junction characterization The use of T-Line for biasing and matching leads the RF signal crossing over this line. Consequently, the tee junction is considered in the design of the PA to avoid frequency shift due to tee junction parasitic capacitance. Fig. 4 confirms that the current flows mainly on the corners. This phenomenon is amplified by the skin effect which is responsible of the high current density concentrated on the edges of the line. A part of the metal in the center of the tee junction is cut in order to decrease the parallel capacitance. The tee junction has an inductive effect with serial resistive losses and a capacitance in parallel at the middle of the junction. This model is taken into account in the simulation schematic. III. PA DESIGN AND MEASUREMENT RESULTS A. PA design description The schematic and the die photography of the PA are depicted in Fig. 5. Two different stacked baluns are placed at the input and the output of the circuit to ensure simultaneously matching and single-to-differential conversion. The common source structure is chosen for its high voltage excursion. The power transistor has a width of 90µm and a width of 48µm for the driver stage. The biasing is performed by the CPW transmission line which ensures a broadband inter-stage matching. The transistors are driven to operate in class AB to reach good trade-off between gain and linearity. The N Sh RF-pad is used. The active area is 0.065mm2 .
3
Vg2=0. 95V
RC Filter
VDD 1=1.2V
RC Filter
200u
50u
Active part 0.065mm
2
90µ 48µ
RC Filter Vg1=0. 95V
RC Filter
50 u
200u VDD 2 =1.2V
VDD1=1.2V
RC Filter Vg2=0. 95V
Fig. 5.
Schematic and die photography of the fabricated 60GHz TABLE I C OMPARISON OF PA S IN 65 NM CMOS TECHNOLOGY FOR 60GHz WPAN STANDARD ReferenceFrequency [2]-60GHz [3]-58GHz [This work]-61GHz
[Tech(nm)] [Foundry] [65][IBM] [65][IBM] [65][STM]
Number of stages 1 3 2
Gain (dB) 4.5 15 8.5
Psat (dBm) 8.5 11.5 7.2
OCP1 (dBm) 6 2.5 4.2
PAE (%) 8.5 11 2.3
Power Consumption (mA@V)
[email protected] 43@1
[email protected]
The fully integrated 65nm CMOS PA is designed and fabricated. An Agilent E83612 vector network analyzer is used to measure S-parameters from 10MHz to 110GHz. The small signal measurements are plotted in Fig. 6. It operates at the desired frequency band because of the accurate modeling of each interconnect junction and accesses to the transistor. At a supply of 1.2V , the PA reaches a gain of 8.5dB at 61GHz in spite of losses caused by power dividing and power combining performed by the baluns. The input and output reflection coefficients are lower than −10dB at 60GHz. The isolation is more than 20dB from DC to 110GHz. The output power as function of the input power is measured to carry out the large signal performances. The PA reaches a Psat of 7.2dBm, an Output 1dB Compression Point (OCP1 ) of 4.2dBm with a weak Power Added Efficiency (P AE). Tab 1 compares performances of PAs found in literature designed with 65nm CMOS technology. C. Interpretation of measurement results The PA was expected to exhibit better linearity performance. The PA does not demonstrate linearity or gain improvement even after performing load and source pull measurements. The two differential stages are biased in the same conditions and have the same power consumption. Retro-simulations enable identifying that the two differential stages are not acting in a balanced mode at 60GHz. Simulations exhibit a magnitude difference of 2.3dB (instead of 0dB) and a phase difference of 153deg (instead of 180deg) between the two differential stages. In view of the aforementioned comments, the first half stage operates in the compression region while the second half stage remains in the linear region.
S-parameters (dB)
B. PA measurement results 0
-20
Simulation
-40
S12 S11
-60 5,0E+10
S22 S21 6,0E+10
7,0E+10
8,0E+10
Freq, Hz Fig. 6.
Measured S-parameters at (Vgs , Vds ) = (0.95V, 1.2V )
IV. BALUN CHARACTERIZATION AND OPTIMIZATION The balun is measured using only a general two-port network analyzer. The end of the primary and the secondary are connected to ground. The transformer exhibits high coupling (more than 0.8dB). Due to the limit of this measurement setup, the single-to-differential conversion performances are not extracted. To understand the reason for this unbalance, 3Delectromagnetic simulations are performed. Therefore, the magnitude of electric field and the magnetic field are probed at the cross section AB (cf. Fig. 7.a). A single RF-mode is applied at the input of the balun. According to Fig. 7.a, the electric field is the responsible for this imbalance. It is due to high capacitive coupling between the primary and the secondary and between the primary and
4
160
E
E H
Optimized balun CMRR (dB)
20*log|E|, 20*Log |H|
RF input
120
80
Typical balun
40 30
The typical balun
60
90
120
Frequency (GHz)
Distance (um)
(a) E and H distributions in a typical balun
(c) The simulated CCMR
160
E
0
Simulated with an optimized balun
9
120
C
80
OCP1= 6.8dBm
7 5
Measured with a typical balun
OCP1= 4.2dBm
3 1
40
-1 30
The optimized balun
60
90
Distance Di t ((um) )
(b) E and H distributions in an optimized balun
Fig. 7.
E H
Pout (dBm)
20*log|E|, 20*Log |H|
RF input
120
-6
-3
0
3
6
9
Pin (dBm)
(d) The optimized balun impact on the output power of the PA
Comparison between a typical and an optimized baluns
the substrate. The retrieved energy by each half secondary is unequal. This phenomenon is always located in one turn balun and can be lowered: • by decreasing the capacitive coupling to the detriment of the coupling coefficient. • by interleaving the primary and the secondary to improve the symmetry coupling [5]. This method lowers the resonance frequency and increases the coupling area with the high-loss substrate. Unlike the electric field, the magnetic field is distributed symmetrically to the secondary because of the constant current crossing over the primary. An original idea to improve the balance performances of this balun is proposed. It consists in adding a serial capacitor at the end of the primary (cf. Fig. 7.b). This capacitor compensates the coupling (previously discussed). It also forces a non-zero voltage at the end of the primary to be coupled with the secondary at the resonance. Hence, a symmetric distribution of the electric and the magnetic fields in the secondary is set. Typically, the Common Mode Rejection Ration (CM RR), defined as the ratio between the differential mode and common mode, is calculated to evaluate the single-to-differential mode conversion balun performance. Fig. 7.c depicts the simulated CM RR of the balun which was used in the PA and the optimized balun. Up to 15GHz, the first balun has a good CM RR. Furthermore, getting higher in frequency induces more losses due to the capacitive coupling and a considerably drop of the CM RR. For the optimized balun, the added capacitor of 87f F allows the balun reaching a CM RR of 30dB at 60GHz. A frequency reconfigurable balun van be designed by tuning the added capacitor.
The optimized balun is integrated instead of the first balun. The PA is able to deliver up to 9.5dBm of output power, and has an OCP1 of 6.8dBm instead of 4.2dBm (cf. Fig. 7.d). V. C ONCLUSION An optimized RF-pad, a CPW T-lines, a tee junction and baluns are customized and considered in the design of a fully integrated 60GHz PA . 65nm CMOS technology from STMicroelectronics is used for the design. Small signal and large signal analysis of the PA are demonstrated. This PA offers a gain of 8.5dB in spite of using baluns at the input and the output of the PA. A critical point of view of the fabricated stacked balun is given concerning balanced-tounbalanced conversion performances. Finally, an optimized high-performance balun is proposed contributing to the design of mmW-frequency circuits. ACKNOWLEDGMENT The authors acknowledge the foundry support provided by STMicroelectronics. The authors thank Conseil Regional d’Aquitaine for the support of NANOCOM test bench. The technical support for testing was provided by M. De Matos. R EFERENCES [1] C.H Doan, S. Emami, A.M. Niknejad and R.W. Brodersen, “Design of CMOS for 60GHz application”, IEEE ISSCC Digest of Technical Papers, pp. 440-53, Feb 2004. [2] A.V. Garcia, S. Reynolds, J.O. Plouchart, “60GHz Transmitter Circuits in 65nm CMOS”, IEEE RFIC Symposium, pp. 1187-1190, June 2008. [3] W.L. Chan, J.R Long, M. Spirito, J.J Pekarik , “A 60GHz-band 1V 11.5dBm Power Amplifier with 11% PAE in 65nm CMOS”, IEEE ISSCC Digest of Technical Papers, pp. 380-381, Feb 2009. [4] S. Aloui, E. Kerherve, J.B. Begueret, R. Plana, D. Belot, “Optimized pad design for millimeter-wave applications with a 65nm CMOS RF technology”, IEEE EUMC, pp. 641-644, Sept 2009. [5] H. Gan, S. Simon Wong “Integrated transformer baluns for RF low noise and power amplifiers”, IEEE RFIC Symposium, pp. 11-13, June 2006.
