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Pulsed Laser SEU Cross-Section Measurement using Coincidence Detectors F.R.Palomo∗, J.M.Mogoll´on, J.N´apoles, H.Guzm´an-Miranda, A.P.Vega-Leal, M.A.Aguirre † † Electronic Engineering Department, Escuela Superior de Ingenieros, University of Sevilla, Sevilla, Spain ∗
[email protected] ∗∗ P.Moreno , C.M´endez, J.R.V´azquez de Aldana †† †† Spanish National Laser Center, University of Salamanca, Salamanca, Spain ∗∗
[email protected]
Abstract—Pulsed laser testing is a useful technique for an accurate inspection of potential weak zones in a layout of an integrated circuit. A laser pulse can provoke a similar effect as a particle hitting with the advantage of a perfect location of the hitting point. The present work describes a general method to determine a Pulsed Laser Single Event Upset (SEU) CrossSection over digital circuits by means of counting statistics. The technique is based on a coincidence detector that count fault events by comparing synchronous outputs of the digital circuit under test and a replica of the design running on a control FPGA. A correspondence map, previously generated by injection fault analysis techniques on the replica, establishes a one-way correspondence between output patterns and each bitflip. With this scheme, the SEU is detected dynamically just using a comparison between the running model and the circuit. Index Terms—Pulsed Laser, SEU Cross Section.
I. I NTRODUCTION Ulsed laser technique is a promising method for the test of integrated circuits emulating certain radiation effects with the main advantage of the precision in time and location. Using laser technique it is possible to induce charge in the very precise location of the layout and discover the weaknesses of the transistor distribution. Many researchers are making a huge effort to know the distance between the ion track and the charge deposition by means of a pulsed laser. This work goes in the direction of an extension of the methodology to the analysis of non structured digital circuits. The measurement of SEU cross section in digital VLSI circuits using the pulsed laser technique, [1], [2], [3], can benefit from coincidence detection techniques. The SEU cross section measurement with a pulsed laser and the coincidence technique means a laser sweep of the chip under test, registering all the output differences with a replica chip and analyzing them as possible SEU events. For each sweep the laser energy is constant, monotonically increasing for successive sweeps. A test platform has been designed that uses a synchronized “golden” replica of the target being illuminated to check the chip under test output pins for errors after each hardware clock cycle. Previous works by Koga et al. use a similar approach in radiation tests of microprocessors in particle accelerators experiments [4], [5], [6] . We propose a new methodology to experimentally obtain the SEU pulsed laser cross-section of complex digital electronic circuits.
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The golden replica of the circuit is implemented on a field programmable gate array (FPGA) using a hardware description language (HDL). This improves the flexibility of the method because any other digital system can be tested using the same control platform, only the high level description of the circuit is needed. When there is a difference in the outputs between the golden replica and the target, it is considered that a SEU has been detected. This paper is organized as follows: Section II describes the proposed methodology to count the number of events under laser illumination in case a HDL description of the test chip is available. Section III address a case study to validate the methodology using an ad-hoc chip with well known output patterns. Section IV explains a pulsed laser cross-section experiment on the test chip to calculate the cross section. II. P ROPOSED M ETHODOLOGY A method to experimentally obtain a pulsed laser SEU cross section for a SRAM cell is detailed in [7]. The procedure basically consists of integrating sensitive areas over an image of the target computing the total area of the laser spots inducing upsets. In [8] there exists also a theoretical definition for the laser SEU cross-section in terms of the heavy ion cross section. Another method to experimentally obtain the SEU laser cross section for SRAM memories is followed in [9], where the target area is swept by the pulsed laser and the crosssection is defined in a similar way as in the ion radiation tests as the number of memory errors multiplied by the area of the target and divided by the number of total pulses. The cross-section calculation implies the measurement of two observables: the pulse fluence, [9], (or equivalently, a number of pixels associated to bit flip per scanned area as in [8]) and the number of events, N (E), with E the pulse energy: N (E) (1) σ= F luence The pulse fluence (or the number of ”bitflip” pixels per scanned area) are easily measured with now standard pulsed laser and image analysis equipment [1].
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In this paper we present a new methodology for measure the number of events, N (E). The methodology is based on three consecutive steps: • Generation of the faulty outputs to bit flip correspondence map. • Coincidence Experiment. • Pattern Matching. This procedure can be used with any digital circuits if it is available a HDL description of them. Previous works related with testing SRAM cells, [9], shift registers, [10], or microprocessors, [6], are specific for each circuit type. A. Generation of the Correspondence Map When computing the number of induced faults (N (E)) in a radiation (or laser illumination) test experiment, it is very important to be able to establish an one-way relation between the observed upsets and the causing bitflip. It is usual to find several output errors delayed in time caused by a single bitflip when testing relatively complex integrated circuits instead of SRAM memories. In this cases, only one fault must be computed. The author [6] solves the problem for microprocessors using a stop-and-reset procedure when a fault appears . However, we consider that it is more reliable for cross-section calculations to run freely the complete set of stimuli while the system records “on the fly” all the output errors. For a complex digital circuit the observed faults are nonexpected output signals. It is mandatory to establish a oneway correspondence between the induced bitflip and the faulty outputs triggered by the bitflip. In order to resolve these cause-effect relationships, it is mandatory to perform a fault injection analisys before the laser test: to inject faults in the circuit and observe the error patterns in the outputs running the same test bench to be used in the laser experiment. It can be done by simulating the HDL description of a digital circuit using a software like Modelsim. Nevertheless, it is not the best solution because it results in a very time consuming method for most of the interesting digital circuits which are made up of thousands of flip-flops and logical gates. For large and complex digital circuits like logical automata, microprocessors or microcontrollers, or whatever circuit being tested, our group have developed the FTUNSHADES hardware emulator [11] [12] [13] for fault injection analysis. FTUNSHADES improves the software simulation by speeding up the test bench to hardware clock frequencies. Using Modelsim or FTUNSHADES leads to the obtaining of the bitflip to faulty outputs correspondence map which associates a single bit-flip with the corresponding error pattern in the outputs of the tested circuit. B. Coincidence Experiment For testing a general digital circuit we use the approach of a logical coincidence experiment. The digital chip under test and a replica chip run synchronized with the same clock. A controller observes the outputs of both test and replica chips and compares them at every clock cycle.
In case of any dissimilarities between the outputs is recorded, the controller generates a warning system recorded in a host log file. The log file contains specific data about the mismatching outputs and the clock cycle when the fault appeared in the output port. Starting with the HDL description of the digital chip under test it is easy to configure a FPGA as a replica chip. The controller can also be implemented from its HDL description inside a FPGA. The platform for the golden replica and the controller in the laser test is a single PCB with a Xilinx Spartan3 FPGA onboard. The PCB provides 3x40-pin sockets to connect one or more dongles carrying the target chip to be illuminated and an USB port to connect the test platform to the host. A custom-made software runs in the host computer allowing the user to remotely control the experiment. The control system in the board side is a finite state machine described in VHDL (Verilog HDL) and synthesized in the FPGA which also includes a replica of the target chip (described in VHDL) called golden. This important feature makes possible to test whatever digital circuit with minimal modifications, just replacing the target dongle and synthesizing, for the FPGA, the VHDL or Verilog hardware description of the digital circuit under test. A set of stimuli is sent to both the target and golden replica of the chip and a continuous comparison of the outputs is enough to detect SEU and Single Event Transient (SET) effects dynamically. The control system is able to limit the current from the source in order to avoid internal damage if a single event latch-up (SEL) is detected. C. Pattern Matching The log files generated in the laser radiation test are analyzed using a custom software lexical analyzer (lexer) in the host computer. The lexer takes previously calculated output patterns from the correspondence map and search for them in the log file. For each pattern found, the lexer counts one bitflip occurred during the radiation test. The final result is the account for the N (E) term in the cross-section calculation. In the next sections III the methodology is applied to a full custom design including a case study. III. A C ASE S TUDY A target microchip has been completely designed by the authors and its functionality is focused on observability of internal SEE, the test circuit has been designed to minimize the number of masked faults. The circuit consists of two different blocks, the first is a 32 bit shift register (SR) and the second is made up of four parallel to serial shift registers (PS). These two blocks are connected by XOR gate arrays that combine the 32 bits of the SR and generates 8 bits that are captured by the PS’s in parallel and sent in serial mode to the outputs of the chip (Fig.3). A special signal (‘Ena’) enables the parallel load of the PS’s. The chip was designed in a 0.5 microns and two metal layers technology. The low density of metal tracks allows a front-side study of the target.
TARGET BOARD
OUTPUT
GOLD RUN (FPGA)
P O WE R PO R T
CLK
G O LD E RU N
CLK
US B P OR T
CLK
TESTVECT
FP G A
CONTROL SYSTEM (FPGA)
CO NTRO L S YS T EM
FIFO OUT
TEST TARGET (F77T)
E EP R O M
OUTPUT
CONTROL BOARD
CONTROL BOARD
FIFO IN
TARG E T BO ARD
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CONTROL BOARD
Fig. 1. From left to right: Schematics of the coincidence detector, showing the Gold Run design configured in an FPGA, the system control logic, also configured in the same FPGA, and the target board with the MOSIS F77T target chip. All the three electronic systems works synchronized by the same clock signal. In the center there is a detail of the general layout. In the right, a photography of the control board FTUSB.
SLAVE FLIP-FLOP
CLOCK BUFFER
CLOCK BUFFER
MASTER FLIP-FLOP
MASTER FLIP-FLOP
SLAVE FLIP-FLOP
Fig. 2. Left: Electronic Schematic of the master-slave target flip flop. Transistors Pairs T4C4, T8C10, T6C8, C10C12 and C11 are sensitive to pulsed laser induced failures. Right: 50X Dark Field image (for enhanced contrast) of the target flip-flop.
The whole control system with the golden replica were stimulated as in the real experiment under the VHDL simulation software ModelSim. This software allows to emulate the bitflips by forcing some signals with a logic value. The stimuli consist of applying clock signals to the SR and PS registers introducing a ’0’ chain in the SR. After shifting the 32 bits, an enable signal (Ena) is activated and the PS registers are loaded in parallel with the XOR outputs. The time needed to fill with logic ’0’ the 32bit SR is 64 iteration cycles (or system cycles) and 4 extra cycles to accomplish the parallel load operation. The “68 iteration cycle” test bench is controlled by the coincidence detector and is repeated continuously. This case study has been focused on a single flip-flop analysis to check the sensitive areas of the layout and to perform a laser cross-section study. Since it is a full custom design, the exact location of each transistor in a flip-flop can be easily found in the layout. Fig.2 shows the schematic of a flip-flop at the transistor level.
The flip-flop chosen to be illuminated in the laser test corresponds to the number 30 in the main 32bit SR. The goal of the laser test was to flip the bit 30 to a logic ’1’. Obviously, the continuous shifting of the SR will put the flipped value in the output (bit 32) 2 cycles after the injection. At that moment, the coincidence detector records an event because the golden SRout presents a logic ’0’ while the target SRout presents a logic ’1’. There is another possible path for the flipped bit to reach an output. There exists a combinational logical path through the XOR arrays that connects the SR bits with the serial input of the PS shift registers by mean of the fourth bit in the 8bit XOR outputs. Under normal operation, an all-time ’0’ is observed at the PS registers outputs. However, a bit flip in SR will put a logic ’1’ in the PS registers inputs for several cycles (until the flipped bit leaves the 32bit SR). This qualitative analysis is possible since the circuit is not complex, however, for more complex digital circuits like
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Fig. 4.
ModelSim simulation Case 1.
Fig. 5.
ModelSim simulation Case 2.
32 bits SHIFT REGISTER
SRin
SRout
( SR )
PS register because the parallel load enable happens before, overwriting the registers with logic ’0’. As can be seen in Fig.5 the SEU is only detected in the SRoutput.
32 bits
Bit 4 Parallel to Serial Register ( PS)
XOR
XOR
matrix
matrix
8 bits
8 bits
Bit 4
Parallel to Serial Register ( PS)
8 bits
Parallel to Serial Register (PS)
IV. T HE E XPERIMENT 8 bits Parallel to Serial Register ( PS)
PS 2 out
PS 1 out
Fig. 3. Schematics of the logical waterfall implemented as VHDL design in the Gold FPGA and built in the digital target chip.
microprocessors, the only way to know about the evolution of the injected fault is to simulate the effect carefully in order to obtain the correspondence map between the observed faulty outputs and the radiative induced bitflip. The simulation results for the test vehicle are shown with the coincidence detector response. In Figs. (4)-(5) it is observed the behavior of the system after the bit flip injection. When the bit-flip is injected in the first 32 iteration cycles, the response is the one shown in the Fig. 4, but when the bitflip is injected later, the fault never reaches the output of the
NOTA: DE AQUI EN ADELANTE HAY QUE REPASARLO TODO For the experiment it were used the facilities at Spanish National Laser Center [18]. The selected laser system is comprised of four stages, all coming from Spectra Physics. The first stage is a Nd:YAG Millenia laser pumping a second stage, the Ti:Sapphire Tsunami laser. The third stage is a Spitfire CPA amplifier, pumped by a fourth stage, an Evolution Nd:YLF laser. The full system is able to generate 110 fs pulses, at 795 nm wavelength, with a maximum of 1 KHz repetition rate and 1 mJ/pulse of peak energy. The optical chain after the laser source has a half wave plate plus a vertical polarizer to attenuate the pulse energy (laser output gives horizontal polarization). Neutral filters, in particular ND1.5 and ND4 can be interposed in the laser path. At the end of the optical chain there is a 50x focusing microscope. Without the neutral filter,s the attenuation factor is determined as 2.74x10 −5. The sweep experiment was made without the neutral filters. The sweep is made with a motorized
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Fig. 6. Left: Millenia Pump Laser, Nd:Vanadate, CW, 532 nm, 5W; Tsunami Femtosecond Laser, Ti:Sapphire, 795 nm, 0.8 W, Mode Locked 80 MHz, Pulse Width < 100 fs; Evolution Pump Laser, FD.Nd:YLF, Q-Switched, 527 nm, Repetition Rate 1KHz, Power >6W, Pulse Width ∼ 100 ns; Spitfire Regenerative Amplifier, Repetition Rate 1KHz, 1 mJ/pulse Energy, Pulse Power 10 GW. Right: Photography of the laser system.
Femtosecond Laser Source 120 fs @ 795 nm, 1 KHz
CCD Camera Computer
Beam Splitter Test Chip F77T
Halfwave plate Polarizer Shutter Neutral Density filters Focusing lens 3D motorized stage
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Fig. 7. Left: Details of the optical channel and readout camera. The optical channel has a polarizer set and several neutral density filters to attenuate the laser pulse energy. The CCD camera gives a infrared image to see the target and the laser spot for focusing adjustments. Right: Photography of the device under test, attached to the 3D motorized stage. The device under test comprises the control board (in the photo center) and the target board (just under the microscope objective).
platform sustaining the chip under test. As a compromise between the laser dwell time and vibration damping it was selected a 300 μm/s sweep speed. The laser spot draws a zigzag pattern on the flip flop sweeping along the larger dimension (50 μm) , moving at steps of 1 μm along the shorter dimension (width, 20 μm), see Fig.2, right image. The accelerations and stops of the platform motors occur out of the flip-flop sensitive area so there are no SEU’s during nonuniform sweep. The controller circuitry is totally out of the laser field of view, so it is not possible to produce systematic errors with the laser in the coincidence detector. Misalignments and vibrations from a too fast sweep are corrected on going thanks to the advanced indicator. The laser dwell time comes from the formula: Dwell T ime =
Sweep Length vsweep
(2)
The sweep length to consider is 60 μm . In that case, with sweep speed of 300 μm/s, formula (2) gives a dwell time of
200 μs on the track. The amount of pulses in a sweep is : Laser P ulses = Repetition Rate · Dwell T ime
(3)
or 200 pulses in a 200 μm track, i.e., 1 laser pulse per μm of track. A typical sensitive area in the target flip-flop is a square of 1x1 μm 2 , so the dwell time selected assures only a pulse in a sweep over each sensitive area of the flip flop. In any case, the flip-flop in the Shift Register change its state at a 3 MHz clock rate, so there is guarantee that there is a one to one relation between each laser pulse and each bit-flip. The output pattern associated to a bit flip (or SEU) is a logic 1 in the Shift Register output and four consecutive logic 1 in the outputs of the pair of parallel to serial converters, 28 clock cycles after. The Event count vs pulse energy is very similar to a reliability test, so, from the literature [19], we try a Weibull fitting to experimental data. For Weibull fitting we use linear regression analysis in Excel. The Weibull distribution for cross
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Fig. 9.
Advanced Weibull Indicator.
VI. C ONCLUSION Fig. 8.
Experimental SEU Count Statistics.
sections is:
x F (x) = A(1 − exp(− )β ) (4) α with A the limiting cross-section. The Weibull distribution can be transformed in a straight line changing variables: ln(ln(
1 )) = βlnx − βlnα 1 − F (x)/A
(5)
so a linear regression analysis is possible to fit the α and β parameters. The analysis results are presented in Figure (8), with A=5350, α=2.575 and β=3.9. V. E XPLOITING AN A DVANCED I NDICATOR Considering uniform scan and constant speed in the laser beam, the sensitive area receives a constant number of laser pulses. In this case, the sensitive area is not a RAM cell but a flip-flop in a Shift Register. In this experiment, approximately three laser pulses fall in a 1μm 2 sensitive area. One data is in each flip-flop for a maximum period of 1/3 MHz-1 =0.33 μs. Due to the system structure, each flip-flop generates an output pattern identified by the coincidence detector as has been described earlier. The time of flight of the laser over an area of 1μm 2 is 3.3 ms, much greater than 0.33 μs which is the period of the Shift Register clock. The coincidence detector is able to resolve each single error and communicate the result to the host. Assuming that no event is lost in communications, the size of the output log file is roughly proportional to the number of events detected in the system and suffered by the target. This is a very useful tool provided it gives the user important information related to the experiment in a quick look. The user can follow if the conditions of the experiment maintains in the appropriate margins because in other case the curve obtained with the sizes of all files would be far different from a Weibull fitting. If so, the corresponding logs can be ruled out and the test repeated. Although the curve obtained is not exactly the final curve, it can be seen that is very close to it and can report important information from the first sight, see Fig (9).
We present experimental data for a pulsed laser SEU CrossSection, using coincidence detectors and techniques inspired from radiation experiments. The proposed methodology is appropriated for VLSI digital circuitry because implies a coincidence test between the faulty circuit outputs and its FPGA replica. The experimental Event counts vs E p are shown and it is proposed a comparison in terms of relative fluencies. The use of FPGAs permits to test different digital designs over the same platform, only replacing a dongle carrying the IC under test. VII. ACKNOWLEDGMENTS The authors want to thank to the project EMULASER (PNE-034-2006) funded by the Centro para el Desarrollo Tecnol´ogico Industrial (CDTI), of the Spanish Industry Ministry in which context has been developed this work. R EFERENCES [1] S.Buchner, Laser Simulation of Single-Event Effects: A state of the art review, ARL-CR-185, Army Research Laboratory, March 1995. [2] J. S. Melinger, S. Buchner, D. McMorrow, W. J. Stapor, T. R. Weatherford, A. B. Campbell, and H. Eisen. Critical evaluation of the pulsed laser method for single event effects testing and fundamental studies, IEEE Trans. Nucl. Sci., vol. 41, p. 2574, Dec. 1994. [3] D.Lewis, V.Pouget, F.Beaudoin, P.Perdu, H.Lapuyade, P.Fouillat, A.Toubul. Backside Laser Testing of ICs for SET sensitivity evaluation, IEEE Transactions on Nuclear Science, vol.48, n6, Dec. 2001, pp 2193-2201. [4] R. Koga, W. A. Kolasinski, M. T. Marra, W. A. Hanna,”Techniques of Microprocessor Testing and SEURate Prediction”, IEEE Transactions on Nuclear Science, vol 32, n 6, December 1985, 4219-4224. [5] J. Cusick, R. Koga, W. A. Kolasinski, C. King, ”SEU Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors”, IEEE Transactions on Nuclear Science, vol 32, n 6, December 1985, 4206-4211. [6] J. H. Elder, J. Osborn, W. A. Kolasinski, R. Koga, ”A method for characterizing a microprocessor’s vulnerability to SEU”, IEEE Transactions on Nuclear Science, vol 35, n 6, December 1988, 1678-1681. [7] P.Fouillat, V.Pouget, D.McMorrow, F.Darracq. Fundamentals of the Pulsed Laser Technique for Single Event Upset Testing, Proceedings of SERESSA 2006, 27-30 November 2006, Centro Nacional de Aceleradores, CNA, Sevilla, Spain.
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