NO-RACE CHARGE RECYCLING COMPLEMENTARY PASS TRANSISTOR LOGIC (NCRCPL) FOR LOW POWER APPLICATIONS I
A. Abbasian', S.H. Rasouli', A. Afiali-Kusha' and M Nourani2 IC Design Laboratory, Electrical and Computer Engineering Dept., Universily of Tehran, Tehran, Iran 'Department ofElectrical Engineering, University of Texas at Dallas Emails: {abbasian. hrasouli)@ece.ut.ac.ir,
[email protected],
[email protected]
ABSTRACT A novel logic family called No-race Charge Recycling Complementary Pass transistor Logic (NCRCPL) has been proposed and analyzed NCRCPL consumes less power with smaller delay compared to the previously reported logic families based on charge recycling. It has an additional benefit of reduced sensitivity to signal skew. Using new regenerator in NCRCPL leads to complete elimination of controller in the circuit, hence the number of transistors was greatly reduced. Considerable improvements in the parameters are confirmed by simulating a two input NAND gate and a full adder using similar styles.
..
logic family is that for a 2-input NAND when both inputs are high, short circuit paths exist in the CPNCL structure leading to high power consumption. In this work, we propose a new logic style called No-race Charge Recycling Complementary Pass transistor Logic (NCRCPL) that dissipates less power with smaller delay compared to these logic families. It has an additional benefit of reduced sensitivity to signal skew. In,Section 2, the operation principles of CRDL, HRDL, CPNCL, and NCRCPL are described and compared. Section 3 contains simulation results for a 2-input NAND and a full adder while the summary and conclusions are given in Section 4.
1. INTRODUCTION
2. CIRCUIT CONCEPT AND OPERATION
One ofthe most important concerns in VLSl design is to achieve low power with optimum performance. Several charge recycling
A 2-input NAND gate implemented in CRDL and HRDL are illustrated in Figure 1. HRDL uses NMOS cascode logic as a
logic techniques have been proposed to reduce power consumption with short delays. These families have two phase of operation, namely, pre-charge and evaluation phases. The recycled charge in pre-charge phase is used in the second phase. This family ideally lowers power consumption by 50% when compared lo conventional dynamic circuits. One of the charge recycling logic styles is called Charge Recycling Differential Logic (CRDL) [Z]. In this technique, PMOS transistors with threshold voltages higher than half V a are required to eliminate conducting paths from Vddto output nodes during the pre-charge phase. A high voltage (Z-220) is needed for N-well bias to increase the threshold voltage of the PMOS transistors. Furthermore CRDL suffers from pre-evaluation problem due to undesired conducting paths in NMOS pass-gate logic for invalid input conditions. In order to solve the pre-evaluation problem of CRDL, a HalfRail Differential Logic (HRDL) has been proposed [3]. The idea is to insert a control circuit between the differential pre-charge (diff-pre) circuits. Here, every diff-pre circuit should have its regenerator accompanying a control circuit, which not only degrades the speed but also increases the power consumption [SI. Additionally, HRDL suffers from a high sensitivity to the signal skew. In addition, in the presence of the signal skew, the preevaluation problem is not solved by this logic style [SI. Recently another logic style, called Modular Charge Recycling Pass transistor Logic (MCRPL) has been proposed which has less power delay product than those of the previously reported charge recycling logic families [4]. MCRPL consists of two types of stages: odd and even. Here, the regenerators are used only in the even stages and, hence, odd stages don't have suitable output swing. Another logic family, called CMOS Pass-gate No-race Charge recycling Logic (CPNCL) has been proposed [ 5 ] to solve the output swing problem of MCRPL and the sensitivity to the signal skew problem of HRDL. One of the problems with this
0-7803-7761-31031P17.00 62003 IEEE
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pull-down path for either out or out depending on the differential inputs. Therefore, it should be associated with a regenerator, which pulls the opposite node to V , for proper operation. The circuit in Figure 2(a) is a 2-input NAND implemented with CPNCL. In this structure, for three states of the input signals, namely, 00, 01, and 10, the pre-charge transistors (M5-M8) and signal amplification transistors (M9-MI2) don't participate in the evaluation phase and therefore PxTd is much less than that of the forth state of the input signal. In the pre-charge phase, clk and elk are low and high and the nodes nl and n2 are set to V , and Vdd, respectively. At the same time, the transistors M l and M8 tum on. In the evaluation phase, if the input signal is in the I I state, M9 and MIU turn on, leading to two shofl circuit paths through MIlM9M7 and M3iMIOM8 until M7 and M8 are tumed off. Therefore, the power consumption in this state would be high. Figure 2(b) shows timing diagram of the 2-input NAND implemented by CPNCL. I t is evident from the figure that output delay for the state 11 of the input signal is much greater than delays of the other states. The 2-input NAND implemented by NCRCPL is shown in Figure 3. NCRCPL is composed of three parts, the evaluation part (MIM4), the regenerator pa6 (M5-M8), and the charge sharing part (M9). NCRCPL uses pass transistor logic style which can pulldown one of the W O output nodes and pull-up the other one. Using this logic style lead to a limited output swing, unless a regenerator circuit is utilized. Additionally, the use of the regenerator lowers the delay of the circuit. If traditional regenerators are used as in the previous structures, the circuit will be sensitive to the signal skew in addition to more power consumption. For solving this problem, two new regenerator structures are proposed for NCRCPL. Figure 4 shows these new regenerators. In the structure shown in Figure 4(a), the input signal is used in pulling-up the output node. In the evaluation
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phase, the node 'x' would he connected to either B o r i , whichever is high. Therefore, M5 and M6 have suitable voltage for regenerating output to its proper value. In pre-charge phase, B and; go to Vd% and hence M7 and M8 will tum off and the node 'x' will be high impedance. The regenerator circuit shown in Figure 4@) is proposed for the cases in which the input signal does not have suitable swing.
node. In the evaluation phase, clk goes to V,, and the voltage of 'z'goes io V , The regenerator does not operate until the input signals have valid logic values making the circuit sensitivity to the signal skew significantly smaller. The timing diagram of the NAND gate of Figure 3 is shown in Figure 5 . As is evident from the figure, NCRCPL has uniform behavior in all of input states. The full adder circuits implemented by NCRCPL are shown in Figure 6. This adder would he compared with the adders implemented in other logic styles in the following section.
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-
h
a
-
z b
b
b-
a
(4 Figure 1.2-input NAND (a) CRDL and (h) HRDL
out clk
out
clk
Figure 3.2-input NAND NCRCPL
-
b
b
I
I
ut
b b a clk
b&b &
b
clk
b
b (
our -T
OUI
out
out
out
out
out
(a) @) Figure 4. 2 regenerator structures for NCRCPL logic (a) Regenerator1 and (h) Regenerator2
)
-
out
out
-
b
-
-
b
AALdpL
b -
O"1
b
-
b
t
b&b
-
t
(b) Figure 2. (a) 2-iuput NAND CPNCL and @) timing diagram In the pre-charge phase clk goes to V, M'8 tums off, M'9 tums on, and M'l turn off and thus 'x' becomes a high impedance
-3
-b
3.¶K.,
b i
a !
b
F
.& ' ".+
_ j a i
Figure 5.2-input NAND NCRCPL timing-diagram
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b
b
ci
NCRCPL are shown for signal skews from 0 . h io 0.9ns. As it can be seen, the variation of the power delay product with signal skew is insignificant. In Figure 7, the power delay products of CRDL, HRDL, CPNCL and NCRCPL are plotted as a function of the signal skew. It is clear that NCRCPL power delay product and its variation is much less than othrr logic styles. In Figure 8, the output waveforms for CRDL, CPNCL and NCRCPL logic are illustrated for a signal skew of 0.5ns. Again, NCRCPL has better behavior and less delay.
-..e.CPNCL
-nws
-..--cRDL
-HRDL
=
-~ m~
S
m-.I.
.._ m.
0 .
1 I
-+N I ...m---N2
--c-
CPNCL
7
a
\CI
a
(b) Figure 6. Full adder (a) sum circuit and @) carry circuits
3. SIMULATION RESULTS The performance of the NCRCPL 2-input NAND gate under no signal skew is given in Table 1. P is defined as the average OV. power measured at 50MHz while T, IS the delay defined as the time it takes for the output to reach 90% of its final valuer after the input signal is applied. In our simulation V , is assumed to be 3V. NCRCPLI uses regenerator shown in Figure4(a) and NCRCPLZ utilizes the regenerator illustrated in Figure 4@). Table 2 shows a comparison of the average power and the delay for the 2-input NAND gates implemented using different styles. It can be seen that NCRCPL has a better PxT, than that of others. Also, it has fewer transistors, which is due to complete elimination of controller in the circuit. In Table 3, the average power, delay, and power delay product of 2-input NAND
'I
Figure I. Power delay product of 2-input NAND DCVS, HRDL, CPNCL and NCRCPL
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Table 4. Summary of full adder CRDL,HRDL, MCRPL. NCRCPL
2.18
CRDL
I
MCRPL NCRCPL
I
1.5 1.16
1.02
0.47
I
0.4
0.26
1
0.6
I
0.3
Figure 8. Out put waveforms of 2-input NAND for 0.5 ns input signal skew Table 1. Summarv of 2-inout NAND
State
(uw)
(ns)
(0)
(uw)
(ns)
(fl)
00
42.3
.31
13.1
45.4
.35
15.89
01
42.4
.31
13.14
45.6
.35
15.96
IO
42.4
.31
13.14
45.6
.35
15.96
11
42.3
.31
13.1
45.4
.35
15.89
5. REFERENCES
Table 2. Summary of 2-inputNANDDCVS, CRDL, HRDL, CPNCL and NCRCPL.
I # o f T r I P,,(uw)
I Tdns)
1 PxT,
DCVS
13
173
0.49
85
CRDL
I 13
143
0.42
I 60
HRDL
I2
134
0.59
79
CPNCL
13
96
0.69
66
NCRCPL
9
42.3
0.31
13.1 I
I
PI
A. bellaouar ,M.I.Elmasry “Low-power Digital Vlsi Design Circuit and system’’ kluwer Academic publisher 1995. 121 B.S.kong,J. S. choi ,S. J. Lee and K. Lee “Charge Recycling Differential Lagic(CRDL) for Low Power Application” I. of Solid-state-circuit ,Vol SI,No9,1996. PI S. Y. Cheo, G. A. Rigby, G. R. Hellestrand “Half-Rail Differential Logic.” in ISSCC Dig. Tech. Papers. Feb. 1997, pp. 420-421. 141 S. M. Jung and S. M. Kang “Modular Charge Recycling Pass transistor Logic (MCRPL)”, ), IEE Electronics Letters, March 2000, vol. 36, no.5 pp.404-405. 151 S. M. Yo0 and S. M. Keng “CMOS Pass-gate No-race Charge Recycling Logic” ISCAS 1999. 161 L. G. Heller, W.R. Griffin, I. W. Davis and N. G. Thoma “Cascode Voltage Switch Logic: A Differential CMOS Logic family.’’ in ISSCC Dig. Tech. Papers. Feb. 1984, pp.16-17. 171 A. Parameswar , H. Hara ,T. sakurai “A High Speed, Lowpower, Swing Restored Pass transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications.” Proceeding of custom integrated circuits conference, 1994, pp. 278-281.
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