Low-power implantable microsystem intended to multichannel cortical recording

LOW-POWER IMPLANTABLE MICROSYSTEM INTENDED TO MULTICHANNEL CORTICAL RECORDING Benoit Gosselin, Virginie Simard and Mohamad Sawan PolySTIM Neurotechnologies Laboratory Department of Electrical Engineering, École Polytechnique de Montréal, Canada [email protected] ABSTRACT We present in this paper an implantable massively parallel cortical data acquisition system. The proposed embedded mixed-signal (analog/digital) processing units are intended to be integrated on one chip, which will be flipped and connected on the top of a microelectrode array. Each channel is composed of a Chopper stabilized (CHS) lowpower front-end to remove the 1/f noise, and a mixedsignal compression module using an analog wavelet transform (WT) processor that covers the entire neural signals bandwidth. The proposed front-end is based on a new rail-to-rail preamplifier topology and its circuit simulation under 0.18 µm CMOS process demonstrates a power dissipation less than 25µW per channel. The main application of this medical device is to record action potentials evoked by visual stimuli, but it can be useful for several other cortical recording purposes. 1. INTRODUCTION Recent advances in neuroscience, biomedical engineering and computing power motivated several researchers to propose Brain-Computer Interfaces (BCIs). A typical BCI is composed of a transducer, a signal processing module that translates acquired biophysical signals into control commands, and a controller. A BCI that could acquire and process the activity of a large number of visual area cells in real time would be of great help for a deeper understanding of neural processes underlying vision. Compared to non invasive recording techniques such as EEG-based systems, multiunit cortical recording by microelectrode arrays increases spatial selectivity and enhances information channel capacity [1]. Commercially available microelectrode arrays have been used in several in vivo experiments and monitoring results from implanted animals for more than 50 weeks’ periods have been reported [1]. In addition to the microelectrode array, a typical cortical data acquisition system (CDAS) includes amplifiers, filters and DSP-based processing module for online

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detection and storage. Although available CDASs have succeeded to record and analyze extracellular action potentials for more than 100 channels, they are not suitable for chronic experiments because of their size and the large number of wires required to connect the microelectrodes to the processing stages. This issue has been addressed in new designs by replacing the wires by a dedicated RF link that transmits data and supplies power to the implant [2]. Moreover, building fully implantable systems with good recording quality required active microelectrodes, that is, an integrated circuit, which includes an amplification front-end and a signal processing module, attached to a MEMS (MicroElectromechanical System) using shared substrate or flip chip technology. The latter has the advantage over shared substrate to fabricate independently the electrode arrays and the integrated circuits, thus allowing more flexibility in implementing both parts. The remaining of this paper includes a brief description of the global implantable CDAS in section 2. We present the front-end preamplifier and the data processing module in sections 3 and 4 respectively. Preliminary results are reported in section 5, and conclusions are in section 6. 2. DESCRIPTION OF THE GLOBAL DEVICE Currently, we propose a CDAS dedicated to record a great number of extracellular action potentials from the visual area’s neurons and transmit them using a RF link to an external control unit. Using flip chip technology, the proposed microsystem will be interconnected to a microelectrode array built in our laboratory [3]. This implantable CDAS includes a front-end preamplifier and a signal processing stage (fig. 1). The front-end is composed of one Chopper stabilized preamplifier per channel. All channels are then sufficiently reamplified, multiplexed and directed to a WT block. The end-to-end signal amplification is 80dB. WT’s feature extraction capabilities facilitate compression and noise filtering of the acquired neural signals and improve precision in event detection. WT coefficients are digitized and transmitted to an external controller.

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Embedded processing electronics CHS Preamplifiers

WT Signal Processing

essentially thermal noise in the baseband. The Chopper frequency as been set to 20kHz, slightly above the corner frequency of the preamplifier’s input referred noise PSD. Neural signals bandwidth is within 100Hz – 6kHz.

Microelectrodes array RF transceiver

Ch 1 Ch 2 Ch i

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1

Control Unit

Gain amplifiers

Bidirectionnal RF Data Link

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Fig. 1 Functional architecture of the cortical data acquisition system

The proposed system architecture requires to meet tight power consumption constraints to prevent surrounding cortex tissues from excess rising of temperature. Also, the implant size had to fit the microelectrode array whose area hold within 4mm x 4mm for 100 electrodes. Noise performances are as well of special interest since extracellular signals have very low amplitude, from a few µV to 500µV. Noise reduction techniques have been used to improve the relatively poor noise performances of CMOS technology and decrease the thermal noise generated by the high resistive part of the electrodes impedances. The front-end focuses on limiting the low frequency noise, while the WT block reduces the thermal noise. Moreover, the limitation of the RF data link bandwidth versus the huge amount of data that could be generated by a large quantity of cells, made data compression and implementation of an efficient multiplexing method necessary. We focus in the following sections in describing only the two main modules of the prototype under construction. 3. LOW-POWER FRONT-END The front-end takes advantage of the Chopper stabilization (CHS) technique and other novel mixed-signal design approach to meet the tight requirements of neural amplification. We propose a new rail-to-rail input preamplifier topology, independent of the input stage, improving the input referred noise, power consumption, CMRR and PSRR. Low-power consumption and small area, criteria of the multichannel front-end, may have required important relaxation on other design parameters of the preamplifier, such as input referred noise and offset voltage. Using process independent techniques like CHS addresses this tradeoff elegantly. CHS provides a strong attenuation of low frequency input referred noise and input offset voltage of the preamplifier. This technique has been used in numerous CMOS low noise applications [4] and it is preferred in low voltage applications over the discrete time method [5]. The input signal is modulated by a square wave, preamplified and modulated back to the baseband (Fig.2), while the low frequency noise (Vn) and the preamplifier’s offset voltage (Vos) modulated once by the second multiplier, are translated to the odd harmonics of the square wave and low-pass filtered, leaving

m(t)

m(t)

Vin(t)

A(f)

Vout(t)

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Fig. 2 The principle of Chopper stabilization technique

The 2nd order transfer function amplifier, A(f), shown on fig. 2, needed for optimum offset reduction, results from the cascaded one pole low-noise rail-to-rail input preamplifier and a micropower gm-C 2nd order band-pass filter. The filter architecture, which using weakly inverted transistors and dissipates less than 2µW, will not be elaborate here since the feasibility of micropower continuous-time filter such as gm-C has been extensively proven in literature. The preamplifier is depicted in fig. 3a. To conciliate power consumption and noise constraints, the circuit has been separated in two main blocks: a highpower and high voltage main preamplifier part, and lowpower low-supply subsequent stages. The preamplifier is built with two pairs of complementary P/NMOS transconductors followed by a unity gain buffer. These input transconductors are biased at high DC current (10µA) to meet the input referred noise constraints, while the remaining of the front-end uses micropower blocks made of transistors biased in weak inversion. A lowpower comparator activates the appropriate complementary transconductors, according to the input common mode voltage, to keep the voltage gain constant and extend the ICMR between 0 and the positive supply rail. Its hysteresis characteristic provides a voltage gap of Vonn – (2VDD – Vonp) which prevents the comparator’s output to be unstable. The tripping voltages must be matched to Vonn and Vonp (Fig. 3b). Then, AC coupling made of small capacitors and highly resistive diodeconnected subthreshold transistors (fig. 3a) sets the output common mode voltage of the complementary transconductors to half of VDD(450mV). The differential preamplifier’s outputs is selected from the PMOS or NMOS input stage towards 4 switches, implemented by single MOS transistors, and directed to an output buffer made of 7 transistors. The sel control signal and switches are used to turn off the inactive transconductor, by connecting its bias input to 2VDD or VSS, which splits the static power consumption of the preamplifier by two. With a bias current Ibi of 10µA for both transconductors, the complementary input stage dissipates up to 90% of the total static power of the front-end.

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4. DATA PROCESSING MODULE

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(b) Fig. 3 (a) Main preamplifier, (b) The preamplifier’s gain matched with the hysteresis characteristic of the comparator.

A unique comparator is sufficient to control preamplifiers of several channels. The micropower part of the front-end works under 0.9V (VDD) supply, while the input complementary transconductors are supplied by 1.8V (2VDD). This higher supply overcomes low voltage railto-rail input stage inherent problems as the creation of a “dead zone“ and allows usage of gate-input transistors instead of noisy low-voltage techniques such as bulk driven transistors or dynamic level shifters. Moreover, a higher supply allows using cascode structures that enhance significantly the CMRR and the PSRR of the preamplifier, which are critical for neural amplification.

Wavelet Transform is a powerful tool well-suited for analysis of neural signals [6]. It facilitates the application of data compression algorithms and noise reduction by concentrating most of the signal energy in a few significant WT coefficients so that the majority of other coefficients are near zero. A threshold eliminates these small coefficients representing noise and less important parts of the signal, and then the remaining signal is fed into a compression module. WT is also needed for the detection of events such as action potentials in a noisy signal where several waveforms generated by different neurons are superimposed. Action potentials detection is performed using predetermined threshold on specific frequency bands located with a priori knowledge on waveforms [6]. Since subsequent modules process only the windowed events, the amount of data to be analyzed and transmitted is greatly reduced. The block diagram of the signal processing module is shown at fig. 5. S/H

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Fig. 5 Simplified block diagram of the signal processing module Vbp

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A drawback of WT is that its hardware digital implementation is quite costly in power, thus it is not really suited for an implantable device. We chose an analog continuous WT core that is made of a bank of six band-pass Q-constant filters of which the center frequencies are logarithmically spaced. Since Gaussian filters provide the best time-frequency resolution according to Heisenberg’s theorem, we approached a Gaussian function using methods of rational approximation [7].

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5. PRELIMINARY RESULTS

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(b) Fig. 4 (a) Schematic of the NMOS complementary transconductor, (b) Schematic of the hysteresis comparator

The rail-to-rail preamplifier has been implemented in CMOS 0.18 µm technology. Its power consumption is below 20µW and has an input referred noise of 30nV/√Hz. Corner simulation results allowed to demonstrate that the entire Chopper stabilized front-end

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will not require more than 25µW per channel. The power consumption of the gain amplifier is below 300nW for a gain of 40dB. Table 1 shows the characteristics of the proposed front-end’s main preamplifier. Regarding the data processing, the center frequencies f0 of the WT processor filter bank have been chosen to provide a full coverage of action potentials frequency range (100 Hz to 6kHz) : 0.156, 0.3125, 0.625, 1.25, 2.5, and 5kHz. The filter bank covers the required bandwidth from 100 to 6800Hz, as shown in fig. 6a. The Gaussian function approximation gave a 6th order transfer function (Eq. 1) which results in a good time-frequency resolution while having a relatively small circuit implementation. 0.4786s3 s6 + 2.058s5 + 3.139s4 + 2.537s3 +1.569s2 + 0.5145s + 0.125

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Table 1. Characteristics of the rail-to-rail input main preamplifier

6. CONCLUSION Circuit techniques and analog signal processing methods have been adopted to design very low-power building blocks dedicated to an implantable neural data acquisition system. The proposed front-end CHS preamplifier and analog Wavelet transform are required to enhance the recording quality of massively parallel cortical neural patterns. Reported preliminary results demonstrate the ability to build an acquisition channel with a power budget of few dozens of microwatts. Further research work includes the design of a high sampling rate low-power ADC, a reliable controller and a bidirectionnal RF link. Also, the implementation of a dedicated software is undertaken to reconstruct neural signal received from the implantable device.

Fig.6(a) Frequency response of filter bank (b) Sampling of bands

7. ACKNOWLEDGEMENTS

Before being fed into the ADC, the filtered signals are sampled at the Nyquist rate of each band (fig. 6b), so the samples can be multiplexed into an ADC. The layout of the proposed topology is undertaken and will be submitted for fabrication in the coming months. Fig.7 show the layout of a one channel Chopper modulated front-end. It is composed of the main preamplifier, the on/off preamplifier bias controller, the 2nd order band-pass and low-pass filter, the modulator/demodulator and the hyteresis comparator. The ADC and the data processing module will be integrated in a subsequent version. 213 µm

Main preamplifier

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Turn on/off preamp’s bias

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2nd order band-pass and low pass-filters

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Fig.7 Layout of one channel of the Chopper modulated FrontEnd. One channel’s area is 213µm x 300µm.

The authors would like to acknowledge the financial support from the National Sciences and Engineering Research Council of Canada (NSERC) and the Canadian Microelectronics Corporation (CMC). 8. REFERENCES [1] D.R., Kipke,R.J. Vetter, J.C. Williams, “Silicon-substrate intracortical microelectrode arrays for long-term recording of neuronal spike activity in cerebral cortex”, IEEE Trans. on NSRE, Vol.11, no.2, pp. 151-155, 2003. [2] H. Yu, K. Najafi, “Circuitry for a wireless microsystem for neural recording microprobes,” IEEE EMBS, vol. 1, pp. 761-764, 2001. [3] S. Pigeon, M. Meunier, M. Sawan, “Design and fabrication of a microelectrode array dedicated for cortical electrical stimulation,“ IEEE CCECE, pp.813-816, 2003 [4] Y. Hu and M. Sawan,“CMOS front-end amplifier dedicated to monitor very low amplitude signal from implantable sensors”, Analog Int. Circ. and Sig. Proc.,Kluwer, vol.33, pp.29-41, 2002. [5] C.C. Enz., G.C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization” , Proc. of the IEEE , Vol. 84, Issue 11 , Nov. 1996. [6] E. Hulata, R. Segev, E. Ben-Jacob, “A method for spike sorting and detection based on wavelet packets and Shannon’s mutual information,” J. Neurosci. Meth. 117, pp. 1-12, 2002. [7] L. Baratchart, J. Grimm, J. Leblond, M. Olivi, F. Seyfert, F. Wielonsky. "Identification d'un filtre hyperfréquence par approximation dans le domaine complexe", RT-219, Inria, 1998.

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