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Analytical Model and Current Gain Enhancement of Polysilicon-Emitter Contact Bipolar Transistors Abdelaziz Zouari and Abdel Ben Arab
Abstract—This paper presents an analytical model that simulates the current gain improvement of polysilicon-emitter bipolar transistors based on the effective recombination velocity method. The theoretical framework developed in this paper incorporates the 2-D structure effect of the polysilicon layer with columnar grain boundary, tunneling processes of holes through polysilicon/ silicon interface oxide layer, and nonuniform doping concentration and bulk recombination effects in the single-crystal emitter. The study goes on to derive an analytical expression for the base current density from which the analytical expression of the current gain was then derived. The effect of oxide breakup, at the polysilicon/silicon interface, on current gain was also considered. The dependence of the current gain on temperature was analyzed numerically; the results are in good agreement with experimental data. The approach outlined in this paper allows one to avoid many of the unnecessary simplifications inherent in previous works and to clearly assess the relevance of each physical mechanism. Index Terms—Bipolar transistor, current gain, interfacial oxide, polysilicon emitter.
NOMENCLATURE q k T VT Wsp (Wsm ) Wb (Wpoly ) dg δ ψs Ne Nb SM Sis (Sip ) Nt Tis (Tip ) Vg
Electron charge. Boltzmann’s constant. Temperature. Thermal voltage. Single-crystal emitter thickness for a bipolar transistor with (without) polysilicon contact. Base (polysilicon) thickness. Grain width. Interfacial oxide thickness. Interface potential barrier. Emitter surface doping level. Base doping level. Front surface recombination velocity. Hole recombination velocity at the singlecrystal emitter (polysilicon) side. Interfacial state density. Interface blocking factor on the single crystal (on the polysilicon) side. Hole recombination velocity at the grain boundary.
Manuscript received April 18, 2008; revised July 9, 2008. Current version published October 30, 2008. The review of this paper was arranged by Editor J. Cressler. The authors are with the Applied Physics Laboratory, Department of Physics, Sfax Faculty of Science, University of Sfax, 3000 Sfax, Tunisia (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.2004247
Spoly
Effective recombination velocity (ERV) relative to the polysilicon region. ERV at the poly/mono interface. Sp Sp,ox (Sp,oxf ) Value of Sp relative to the portion of the emitter with (without) interfacial oxide layer. Average value of the ERV at the poly/mono Sp,av interface. Oxide breaking ratio. box Hole concentration in the single-crystal emitter p0 (y) at equilibrium. JpEM (JpEP ) Emitter reverse saturation current density for metal (polysilicon) contact emitter bipolar transistor. RCA devices Those given an RCA clean prior to polysilicon deposition. HF devices Those given an HF clean prior to polysilicon deposition. Hole diffusion coefficient (length) in the Dp1 (Lp1 ) monocrystalline grain. Hole diffusion coefficient (lifetime) in the (Dp2 )τp2 single-crystal emitter. Average hole diffusion coefficient (lifetime) in Deff (τeff ) the single-crystal emitter. Average hole diffusion length in the singleLeff crystal emitter. η Current gain improvement. Pseudograin boundary mobility. μpgb Δ Thickness of the pseudograin boundary. I. INTRODUCTION
P
OLYCRYSTALLINE silicon has often been used in bipolar integrated circuit processes and proved to be efficient in the improvement of switching speed and packing density. In addition, the use of polycrystalline silicon as a diffusion source allows the formation of very shallow emitter–base junctions without the degradation in the transistor’s current gain [1], [2]. A number of previous studies have reported that, compared to conventional bipolar transistors, improvements in current gains that ranged between factors 3 and 30 were obtained [3]–[9]. The authors demonstrated that this gain improvement strongly depended on the kind of surface treatment being used before the deposition of the polysilicon [6], [9]. The current gain of the RCA transistor was reported to be about five times higher than that of the HF transistor, which was given a dip etch in buffered hydrofluoric acid prior to polysilicon deposition [6]. The physical mechanisms that control the current gain have been extensively investigated. It has actually been established
0018-9383/$25.00 © 2008 IEEE
ZOUARI AND BEN ARAB: ANALYTICAL MODEL AND CURRENT GAIN ENHANCEMENT OF BIPOLAR TRANSISTORS
that the injection of the minority carrier into a polysilicon emitter is controlled by a whole range of complex processes: hole transport and recombination in the monocrystalline region, hole transport across the polysilicon/silicon interface, and hole transport and recombination in the polycrystalline region. The transport across the interface has actually been more thoroughly studied, and fairly different accurate models have been developed. This is in part due to the fact that the physical structure of the interface is very sensitive to process condition. These mechanisms have been summarized in four basic models that have different predictions with respect to a decrease in the base current and an increase in the current gain. The first is termed the “oxide tunneling model” [3], [5] and explains the improved current gain by tunneling through a thin interfacial oxide layer. The second is termed the “grain boundary mobility model” [4], [10] and explains the improved current gain by reduced mobility at the grain boundaries in the polysilicon and at the pseudograin boundary at the poly/mono interface. This model predicts a reduction in base current when the density of interface states at the grain boundaries is small. The third is termed the “segregation model” [11], [12] and explains the improved current gain by the presence of a potential barrier at the poly/mono interface due to dopant atom segregation. The fourth (4) is called the “heteroemitter-like model” [13], [14] and explains the improved current gain by regarding the poly/mono interface as a wide-bandgap material which can limit minoritycarrier transport from silicon to polysilicon. Jin et al. [14] have reported, from their experimental results, that the bandgap ΔEg resulting from wide-bandgap material is the main mechanism that can achieve higher current gain with lower temperature sensitivity. In addition, even though considerable theoretical work has been directed to polysilicon-emitter bipolar transistors, most studies seem to have relied on simplified assumptions that might have limited their applicability. In most cases, either the recombination in the single-crystal emitter was neglected [3], [4], [14], [15], or a simplified model for the transport in the polysilicon was assumed [13]–[15], or the grain boundaries were merely considered to be parallel to the n-p junction [10], [16]. In addition, only a few models, such as the analytical model of Ma et al. [17], could explain the transport mechanisms governing the gain improvement. Nevertheless, Ma’s theory is relatively complicated. Within this context, this paper aims to present a simple and comprehensive analytical model to explain the polysiliconemitter bipolar transistors’ current gain enhancement. The grain boundaries in the polysilicon layer were taken perpendicular to the emitter–base junction (columnar grain boundaries). The minority-carrier injection in this region was simply described by an effective recombination velocity (ERV) Spoly [18]. This approach allowed for an accurate description of the complex minority-carrier transport in the polysilicon region by a simple model. The poly/mono interface was described by the same expression of the ERV obtained in [16], including the new expression of ERV established for the polysilicon layer with columnar grain boundaries. The minority-carrier transport in the nonuniformly and heavily doped single-crystal emitter was developed using the average value approach presented in [19],
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Fig. 1. Schematic diagram of a 2-D model of an n-p-n bipolar transistor with a polysilicon emitter, including the physical and structural parameters, symbols, and carrier distribution.
which turned out to give more accurate results. The dependence of the current gain enhancement on the polysilicon parameters and temperature was also discussed. II. ANALYTICAL MODEL A. Base Current Density The present analysis is based on the ERV method. ERV is one of the most frequently used approaches in the literature. It has the advantages of simplicity, flexibility, and straightforwardness. It is particularly useful for it allows the separate modeling of the three different regions, namely, the polysilicon region, the single-crystal silicon region, and the polysilicon/silicon region, which, in turn, allows the selection of the appropriate model that best suits each region. Fig. 1 shows a 2-D schematic structure of an n-p-n bipolar transistor with a polysilicon emitter, including the physical parameters and carrier densities. The emitter consisted of a polysilicon layer, a breaking interfacial oxide layer (widebandgap material), and a single-crystal silicon layer. The holes were injected from the p-base over the junction, cross the segregation potential barrier ψs on the single crystal side, and then tunneled through the interfacial oxide into the polysilicon region. The idea was to obtain the base current density that was equal to the hole current density injected into the emitter at x = (Wpoly + δ + Wsp ). The holistic approach of our model encompasses a wide range of aspects. It covers, for instance, aspects pertaining to the nonuniform doping concentration in the single-crystal emitter (Gaussian profile), the diffusion and recombination in the bulk of the crystal silicon region, the tunneling through the native oxide at the polysilicon/silicon interface, the recombination at both sides and the breaking area of the interfacial oxide, the columnar grain orientation, the diffusion and recombination in the bulk of the grains, and the recombination at the grain boundaries.
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1) Modeling of the Polysilicon Emitter: In our approach, we considered a columnar grain texture for the polysilicon-emitter layer in which the grain boundaries were oriented perpendicularly to the emitter–base junction (see Fig. 1). Similar to the previous works [10], [16] where the grain boundaries were oriented parallel to the emitter–base junction, the polysilicon layer was modeled by an ERV Spoly which was calculated by solving the equations associated with the 2-D continuity and the current transport in the grain volume. An analysis of the performance of a polysilicon-contacted solar cell with columnar grain boundaries has previously been presented by Zouari et al. [18]. The minority-carrier injection in this region was simply described by an ERV Spoly . The same steady-state continuity equation and boundary conditions were used in the present analysis for a polysilicon-emitter bipolar transistor. The ERV Spoly can, therefore, be expressed as follows [18]: 8 sin2 (Ck dg /2) 1 Spoly = · dg Ck2 dg + Ck sin(Ck dg ) k≥0 ⎧D ⎫ ⎨ Lp1 tanh WLpoly + SM ⎬ k k · (1) ⎩ 1 + SM Lk tanh Wpoly ⎭ Dp1 Lk where (1/L2k ) = Ck2 + (1/L2p1 ) with Ck coefficients are the solutions of the transcendent equation:
Ck dg Vg (2) tg = 2 2Ck Dp1 and Dp1 (Lp1 ) is the hole diffusion coefficient (length) in the monocrystalline grain. 2) Modeling of the Interface: Due to the process of depositing polysilicon on the single-silicon emitter, an insulating layer was introduced between the polysilicon and silicon. Its thickness (0 < δ < 2.5 nm) depended on the chemical interface treatment performed prior to the deposition of the polysilicon [6], [9]. When the silicon surface was subject to an RCA cleaning that was immediately followed by polysilicon deposition (RCA devices), a thick oxide layer was formed, and a potential barrier ψs against holes was obtained. The holes were assumed to cross the potential barrier, by thermionic emission, and then to tunnel through the oxide layer. When an HF dip was performed prior to polysilicon deposition (HF devices), a thin oxide layer was then formed. The poly/mono interface can be modeled by an ERV SP that defines the recombination velocity at the right side of the polysilicon/silicon interface, as shown in Fig. 1 and given by [16] SP = Sis + Tis
Spoly + Sip Tip + Spoly + Sip
analysis, Spoly is the ERV given by (1), which characterizes the effect of the polysilicon layer on the behavior of the minority carriers in the crystalline emitter. The effect of a broken-up interfacial oxide layer on the base current is modeled by assuming that the poly/mono interface area can be divided into the following two fractions: an oxidized fraction that had a width δ and that was characterized by an ERV SP,ox (dominated by the oxide tunneling model); and an oxide-free fraction in which the crystal silicon contacted with polysilicon and that was characterized by an ERV SP,oxf (dominated by the nonblocking interface model). The entire interface can be described by an average value of ERV [20] expressed as follows: Sp,av = (1 − box )SP,ox + box SP,oxf
(4)
where box (0 ≤ box ≤ 1) is the ratio of the oxide-free area to the total polysilicon contact area, while box = 0 symbolizes the uniform oxide, and box = 1 symbolizes the oxide-free area at the interface. 3) Modeling of the Crystalline Silicon Emitter: In order to relate the ERV to the base current, it is necessary to model the recombination in the single-crystal emitter region doped with arbitrary concentration. When calculating the base current density, most previous polysilicon bipolar transistor emitter models seem to have overlooked or approximated the bulk recombination (transparent emitter) [3], [4], [14], [15]. This approximation is reasonable in metal-contacted emitters due to the high value of the contact recombination velocity SM [21]. This approximation is, however, not valuable for polysiliconemitter contact due to the much lower value of SP [22]. This has, in fact, been demonstrated by the experimental results relative to devices with a deliberately grown interfacial oxide [23]. It has been shown that, in the case of a shallow emitter, the injected hole current density for any contact recombination velocity S may be accurately calculated by a simple approximate expression using the average value approach [19] that takes the bulk recombination into account. This is expressed in the following: · tanh LWeffs + S = qp0 (0) eff 1 + SL · tanh LWeffs Deff
JpE
Deff Leff
(5)
where
τeff
⎞−1 ⎛W s p0 (y) ⎠ dy = p0 (0)Ws · ⎝ τp2 (y)
(6)
0
⎛
(3)
where Sip and Sis represent the interface recombination velocity at both sides of the interfacial oxide. Tip and Tis represent the “blocking factors” of the holes at the boundaries x = Wpoly and x = Wpoly + δ, respectively. They depend on the physical mechanism controlling the hole flow at the interface. In our
Deff = Ws · ⎝p0 (0) · Leff =
as defined in [19].
Ws
⎞−1 dy ⎠ Dp2 (y)p0 (y)
(7)
0
Deff τeff
(8)
ZOUARI AND BEN ARAB: ANALYTICAL MODEL AND CURRENT GAIN ENHANCEMENT OF BIPOLAR TRANSISTORS
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TABLE I PHYSICAL PARAMETER VALUES
τp2 and Dp2 represent the hole lifetime and diffusion coefficients in the single-crystal region, respectively, while τeff and Deff represent their average values. Leff is the average value of the diffusion length in the single crystal. p0 (y) is the minority-hole concentration which takes the position-dependent doping and bandgap narrowing into account. Replacing the contact recombination velocity S in (5) by SP,av (SM ) and the emitter thickness Ws in (5)–(7) by Wsp (Wsm ), an analytical base current density expression JpEP (JpEM ) for polysilicon (metal)-contacted devices was obtained.
Fig. 2. Polysilicon ERV Spoly as a function of the polysilicon layer thickness Wpoly . Dots represent the result of the single-grain model [25]. The dashed line corresponds to the detailed multigrain model [10], while the solid lines correspond to the columnar multigrain model for different grain widths dg ’s (this paper).
B. Physical Parameters In order to determine the value of the relevant physical parameters, our analytical model used the minority-carrier lifetime, mobility, and the apparent bandgap narrowing physical models [24]. The “blocking factors” of the holes, Tip and Tis , were taken from the models of Ning and Isaac [4] and Ma et al. [17] to calculate Sp,ox and Sp,oxf , respectively. For the sake of simplicity, a uniform doping concentration in the base region was assumed. All the values of the physical parameter used in our analysis are shown in Table I. III. RESULTS AND DISCUSSIONS A. Effect of the Polysilicon Layer on the ERV Spoly In Section II-A1, an analytical expression of the ERV Spoly was derived to thoroughly account for hole injection into the polysilicon with columnar grain boundaries. Fig. 2 shows the variation of Spoly versus polysilicon thickness for different grain widths dg ’s. For the sake of comparison with the previous work (with grain boundaries being assumed to be parallel to the emitter–base junction), the same figure shows the values obtained for Spoly when using the iterative approach proposed by Yu et al. [10] (the dashed line). It can be seen that, for dg = 0.01 μm, the Spoly associated with devices having polysilicon thickness greater than 0.2 μm becomes independent of Wpoly . This can be accounted for by the fact that as Wpoly increases, the majority of the holes injected into the polysilicon layer recombine at the grain boundary. When the grain width dg is more than 0.01 μm, the recombination at the grain boundary is less important, and the minority-carrier holes can reach the surface of the poly and get
Fig. 3. ERV Sp as a function of the interfacial oxide layer thickness δ for different potential barrier ψs values and different rates of the breaking oxide area box . Sis = 2 × 103 cm/s and Wpoly = 0.4 μm.
recombined, thereby decreasing Spoly with an increase in the thickness of poly. For dg = 1 μm, the recombination at the grain boundary can actually be considered negligible since the Spoly values are similar to those relative to the polysilicon region formed by a single grain [25]. It can also be noted that all the Spoly values of the columnar structure (the more realistic structure which is considered in this paper) are greater than those calculated by Yu’s approach (detailed multigrain model). B. Effect of the Interfacial Oxide Layer on the ERV Sp,av In Fig. 3, the ERV Sp,av , calculated from (4), is plotted as a function of the oxide thickness for a fixed polysilicon thickness (Wpoly = 0.4 μm) and different potential barriers ψs ’s. For devices with uniform interfacial oxide (box = 0), Sp,av tends asymptotically to a fixed value which corresponds to Sis (Sis is the recombination velocity at the interface at the right
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Fig. 4. Dependence of current gain improvement η on the interfacial oxide layer thickness δ for different rates of the breaking oxide area box . Sis = 2 × 103 cm/s and ψs = 20 mV.
side) since the blocking action of the oxide layer increases with increasing δ. On the other hand, as δ decreases, the transport in the polysilicon, together with the thermionic emission (due to the effect of the potential barrier ψs ), becomes the limiting process. The Sp,av approaches the value (Spoly + Sis ) given by the nonblocking interface (two-region) model [4] (the upper curve in Fig. 3). For devices with discontinuous interfacial oxide (box = 2% and 15% for example), Sp,av tends asymptotically to box Spoly + (1 − box )Sis with increasing δ (see Fig. 3). It becomes evident that, for a thick interfacial oxide, and apart from the very early stages of oxide breakup (box = 2%), the overall recombination velocity Sp,av is dominated by the second term in (4). C. Effect of the Interfacial Oxide Thickness on the Current Gain Improvement The dependence of the current gain improvement η(η = JpEM /JpEP ) on interfacial oxide thickness is shown in Fig. 4 with uniform (box = 0) and breaking oxide (box = 2% and 15%) areas. For a small oxide thickness (δ ≤ 0.7 nm), the curves are identical, and the oxide breaking area has no effect on the current gain. When the oxide thickness exceeds 0.7 nm, the curves become separated. This means that, in a device with a brokenup interfacial oxide, the majority of the hole current flows through the oxide-free regions. Thus, compared to devices with uniform oxide, the current gain improvement of devices whose interface is 15% oxide free decreases by a factor of about 12. For this reason, Post et al. [20] attributed the increase in the base current (decrease in the current gain) of the RCA device, when the interface anneal temperature is increased, to the increase in area that oxide-free interface portions underwent. D. Dependence of the Current Gain on Temperature Figs. 5 and 6 show the dependence of the current gain on inverse temperature for RCA and HF devices with Wpoly =
Fig. 5. (a) Current gain for RCA devices versus inverse temperature for different potential barriers ψs ’s. δ = 1.48 nm and Nt = 1 × 1011 cm−2 . The theory is in agreement with the experimental results [14] for ψs = 7 mV. (b) Current gain for RCA devices versus inverse temperature for different interfacial state densities Nt ’s. δ = 1.48 nm and ψs = 7 mV. The theory is in agreement with the experimental results [14] for Nt = 1 × 1011 cm−2 .
Fig. 6. Current gain for HF devices versus inverse temperature using the pseudograin boundary mobility model. Nt = 1.3 × 1013 cm−2 .The interface hole mobility μpgb is assumed to be proportional to T −n . The theory is in agreement with the experimental results [14] for n = 0.75.
0.4 μm, respectively. We assumed that the base was not subject to freeze-out [26] and that the lifetime and carrier mobility were independent of temperature [27].
ZOUARI AND BEN ARAB: ANALYTICAL MODEL AND CURRENT GAIN ENHANCEMENT OF BIPOLAR TRANSISTORS
For RCA devices (δ = 1.48 nm with uniform oxide area [14]), we used the oxide tunneling and thermionic model [17] in which the thermionic emission over the segregation potential barrier and the recombination at both sides of the interfacial oxide represented the two major transport mechanisms that the study of the current gain as a function of temperature used. Fig. 5(a) shows that, at higher temperature, the thermionic emission can cause the current gain to be more sensitive to temperature when the potential barrier ψs increases. However, Fig. 5(b) shows that, at lower temperature, the recombination at the interfacial oxide can achieve higher temperature sensitivity for the current gain through the interfacial recombination velocity Sis ∼ Nt · T −3.4 , when the interfacial state density Nt increases. The theory is in excellent agreement with the experimental results of Jin et al. [14] over the whole temperature range for Nt = 1 × 1011 cm−2 and ψs = 7 mV. For HF devices, a fit cannot be made to the measured current gain with the oxide tunneling and thermionic model, which implies that this interfacial model cannot explain the experimental temperature dependence results. Fig. 6 shows the experimental data of Jin et al. [14], as well as the modeled current gain, using the pseudograin boundary mobility model (Tis = Tip = VT (μpgb /Δ) [20]). The interface hole mobility μpgb is assumed to be proportional to T −n (μpgb = AT −n ), as proposed by Post et al. [20]. The n = 0 case corresponds to the temperature dependence of a conventional metal-contacted bipolar transistor, whereby the temperature dependence of the current gain is attributed to the difference in the bandgap narrowing between the base and the emitter. An excellent fit to the experimental data can be achieved for n = 0.75 and Nt = 1.3 × 1013 cm−2 . IV. CONCLUSION In this paper, an analytical model, based on the ERV method, to simulate the current gain improvement of polysilicon-emitter bipolar transistors has been developed. The polysilicon layer was considered to consist of a columnar grain structure. The doping concentration in the single-crystal emitter was taken nonuniform with Gaussian profile. Recombination and tunneling at the poly/mono interface, and thermionic emission over the segregation potential barrier were also considered. A simple analytical expression of the base current density was then obtained. It is demonstrated that the ERV approach allows the independent modeling of the polysilicon layer, the poly/mono interface, and the single-crystal region in a way that permits the selection of the appropriate model to be used for each region. The oxide breakup effect, at the polysilicon/silicon interface, on current gain was also considered. The temperature sensitivity of the current gain has been studied; the results are in good agreement with experimental data. Findings from the study of the dependence of the current gain on the physical parameters indicated that the transport mechanism governing the gain improvement depended particularly on the chemical interface treatment performed prior to polysilicon deposition (RCA or HF devices) and the anneal temperature (which controls the oxide-free fraction of the interface).
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ACKNOWLEDGMENT The authors would like to thank S. Anwar of the English Department of the Sfax Faculty of Science, University of Sfax, Sfax, Tunisia, for carefully proofreading and constructively revising this paper. R EFERENCES [1] M. Suzuki, K. Hagimoto, H. Ichino, and S. Konaka, “A bipolar monolithic multigigabit/s decision circuit,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 462–467, Aug. 1984. [2] T.-C. Chen, C. T. Chuang, G. P. Li, S. Basvaiah, D. D.-L. Tang, M. B. Ketchen, and T. H. Ning, “An advanced bipolar transistor with self-aligned ion-planted base and W/poly emitter,” IEEE Trans. Electron Devices, vol. 35, no. 8, pp. 1322–1327, Aug. 1988. [3] H. C. de Graaf and J. G. de Groot, “The SIS tunnel emitter: A theory for emitters with thin interface layers,” IEEE Trans. Electron Devices, vol. ED-26, no. 11, pp. 1771–1776, Nov. 1979. [4] T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of silicon bipolar devices,” IEEE Trans. Electron Devices, vol. ED-27, no. 11, pp. 2051–2055, Nov. 1980. [5] A. A. Eltoukhy and D. J. Roulston, “The role of the interfacial layer in polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-29, no. 12, pp. 1862–1869, Dec. 1982. [6] P. Ashburn and B. Soerowirdjo, “Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, no. 7, pp. 853–860, Jul. 1984. [7] A. Neugroschel, M. Arienzo, Y. Komem, and R. D. Issac, “Experimental study of the minority-carrier transport at the polysilicon—Monosilicon interface,” IEEE Trans. Electron Devices, vol. ED-32, no. 4, pp. 807–816, Apr. 1985. [8] G. R. Wolstenholme, N. Jorgensen, P. Ashburn, and G. R. Booker, “An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations,” J. Appl. Phys., vol. 61, no. 1, pp. 225–233, Jan. 1987. [9] G. R. Wolstenhoolme, D. C. Browne, P. Ashburn, and P. T. Landsberg, “An investigation of the transition from polysilicon emitter to SIS emitter behavior,” IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1915–1923, Nov. 1988. [10] Z. Yu, B. Ricco, and R. W. Dutton, “A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, no. 6, pp. 773–784, Jun. 1984. [11] C. C. Ng and E. S. Yang, “A thermionic-diffusion model of polysilicon emitter,” in IEDM Tech. Dig., 1986, pp. 32–35. [12] B. Jalali and E. S. Yang, “A general model for minority-carrier transport in polysilicon emitters,” Solid State Electron., vol. 32, no. 4, pp. 323–327, Apr. 1989. [13] K. Suzuki, “Unified minority-carrier transport equation for polysilicon or heteromaterial emitter contact bipolar transistors,” IEEE Trans. Electron Devices, vol. 38, no. 8, pp. 1868–1877, Aug. 1991. [14] H.-Y. Jin, L.-C. Zhang, Y.-Z. Gao, and H.-F. Ye, “An equivalent heterojunction-like model for polysilicon emitter bipolar transistor,” Solid State Electron., vol. 47, no. 10, pp. 1719–1727, Oct. 2003. [15] X.-L. Jiang, W.-L. Guo, and Y.-M. Zhang, “A unified model of a poly-Si emitter transistor for various emitter structures,” Semicond. Sci. Technol., vol. 9, no. 5, pp. 1117–1125, May 1994. [16] N. F. Rinaldi, “On the modeling of polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. 44, no. 3, pp. 395–403, Mar. 1997. [17] P. Ma, L. Zhang, B. Zhao, and Y. Wang, “An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. 42, no. 10, pp. 1789–1797, Oct. 1995. [18] A. Zouari, A. Trabelsi, and A. Ben Arab, “Simple analytical solution and efficiency improvement of polysilicon emitter solar cells,” Sol. Energy Mater. Sol. Cells, vol. 92, no. 3, pp. 313–322, Mar. 2008. [19] A. Zouari and A. Ben Arab, “A simple formulation of the saturation current density in heavily doped emitters,” Can. J. Phys., vol. 81, no. 9, pp. 1109–1120, Sep. 2003. [20] I. R. C. Post, P. Ashburn, and G. R. Wostenholme, “Polysilicon emitters for bipolar transistor: A review and re-evaluation of theory and
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experiment,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1717–1730, Jul. 1992. J. A. del Alamo and R. M. Swanson, “The physics and modeling of heavily doped emitters,” IEEE Trans. Electron Devices, vol. ED-31, no. 12, pp. 1878–1888, Dec. 1984. A. Zouari and A. Ben Arab, “Minority carrier transport equation for bipolar transistors with polysilicon emitter contact,” Phys. Stat. Sol. (A), vol. 196, no. 2, pp. 436–449, Mar. 2003. P. Ashburn, D. J. Roulston, and C. R. Selvakumar, “Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-34, no. 6, pp. 1346–1353, Jun. 1987. J. A. del Alamo, S. Swirhum, and R. M. Swanson, “Simultaneous measurement of hole life-time, hole mobility, and bandgap narrowing in heavily doped n-type silicon,” in IEDM Tech. Dig., 1985, pp. 290–293. J.-S. Park, A. Neugroschel, and F. A. Lindholm, “Systematic analytical solutions for minority-carrier transport in semiconductors with position-dependent composition, with application to heavily doped silicon,” IEEE Trans. Electron Devices, vol. ED-33, no. 2, pp. 240–249, Feb. 1986. C. Kittel, Introduction to Solid State Physics. New York: Wiley, 1971, p. 723. S. S. Li and W. R. Thurber, “The dopant density and temperature dependence of electron mobility and resistivity in n-type silicon,” Solid State Electron., vol. 20, no. 7, pp. 609–616, Jul. 1977.
Abdelaziz Zouari was born in Sfax, Tunisia, in April 1972. He received the B.S. and Ph.D. degrees in physics from the Sfax Faculty of Science (SFS), University of Sfax, Sfax, Tunisia, in 1995 and 2003, respectively. Since 2001, he has been teaching and lecturing on physics with the SFS, where he has been an Active Member with the Applied Physics Laboratory, Department of Physics, since 2000. His current research interests include physics and the modeling of bipolar transistors and solar cells.
Abdel Ben Arab was born in Sfax, Tunisia, in November 1958. He received the Ph.D. degree from the University of Toulouse, Toulouse, France, in 1987, and the “Doctorat d’Etat” degree from the University of Tunis, Tunis, Tunisia. He has been a Technical Staff Member with the Applied Physics Laboratory, Department of Physics, Sfax Faculty of Science, University of Sfax, Sfax, Tunisia, since 2000. He is the author or coauthor of 20 papers. His current research interests include physics and the modeling of bipolar transistors and solar cells.
