A visual design environment

A Visual Design Environment* Eric J. Golin, Annette C. Feng, Linus Huang and Eric Hughes Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign

Abstract

an integrated design database using multiple representations; and an explicit representation of design managment information. Several researchers have developed graphical representations for hardware description languages. The graphical representation for STRICT [l] uses structural diagrams and Petri nets to represent behavior. Statecharts, a visual programming language for reactive systems, have been applied to the specification of behavior [2]. EXEL [3] uses interconnected graphic icons to specify the behavioral synthesis process. While vVHDL provides a direct visual representation of VHDL, the above languages use a different computational model and map it into VHDL concepts. Several other systems have included some type of graphical specification of VHDL designs. The AFIT VHDL Environment [4] provides a graphical user-interface for constructing VHDL designs. The proposed AVE system [5] would allow graphical views of multiple levels of a design hierarchy and would mix schematic-like representations with textual VHDL code. Comdisco’s Signal Processing Worksystem [SI (SPW) provides a block diagram editor which allows the user to construct a design by interactively combining components from a library of signal processing components. While supporting some graphical design specification, these systems do not provide a visual syntax for behavioral designs.

This paper describes an approach to hardware design that combines the graphical nature of schematic design systems with the high-level design methodology of hardware description languages. We have developed an environment for the design of electronic systems based on a visual hardware description language. The Visual Design Environment with Objects (or ViDEO environment) allows the user to contruct a design as a graphical program in the vVHDL visual hardware description language. The graphical design can be compiled into a standardized representation, analyzed and simulated.

1

Introduction

Graphical design tools such as schematic capture systems offer a visual approach to building designs from circuit diagrams. Although these diagrams are very useful for describing gate-level designs, complex systems also require modeling of components in terms of behavior. Hardware description languages provide a high-level representation that can be used for documenting, communicating and simulating the design, but at the cost of a cumbersome syntax which obscures the concurrent nature of the design. This paper describes an approach to hardware design that combines the graphical nature of schematic design systems with the high-level design methodology of hardware description languages. We have developed an environment for the design of electronic systems based on a visual hardware description language, called v V H D L (for visual VHDL). The Visual Design Environment with Objects (or ViDEO environment) allows the user to contruct a design as a program in the vVHDL visual hardware description language. The graphical design can be compiled into a standardized representation] analyzed and simulated. In addition to its visual approach, ViDEO contains several novel features, including an open tool integration framework;

‘

The ViDEO Environment

The ViDEO environment consists of an editor for visual designs, a compiler for translating visual designs into the underlying VHDL representation, and commercial tools for analysis and simulation of VHDL designs. The environment components are organized around an object-oriented database, which is used as a repository for design information and to share data between tools. The schema (i.e., structure) for the design database can be divided logically into “subschemas” for the visual designs, compiled designs and simulation models. A message-based control integration mechanism allows the tools to invoke each other. Figure 1 illustrates the abstract architecture of the environment.

*This research is supported by the Texas National Research Laboratory Commission, project #047, and by National Science Foundation grant CCR-9108931

364

1063-6757/93 $03.00 0 1993 IEEE

2

I

COUNIER

I

Figure 1: Architecture of the ViDEO Environment The vVHDL Editor is used to create a visual hardware design consisting of a hierarchically organized collection of diagrams. Each vVHDL diagram is composed of graphical icons, loosely corresponding to VHDL constructs, arranged according to the syntax of the vVHDL language. The vVHDL editor is basically an unstructured graphics editor that has been configured for the vVHDL language. A design is constructed by arranging the appropriate elements into a vVHDL diagram. The editor treats the diagram as a source program, providing operations for editing the picture, rather than the underlying structure. This is analogous to the manner in which a text editor views a C program as a text file. The editor uses the database to store and organize the pictures. Each picture is stored as a single object with links to any subunit pictures. The vVHDL compiler analyzes a vVHDL source program and translates it to a compiled form consisting of an abstract, object-oriented representation of VHDL which is stored in the database. A textual VHDL program is also generated for use with VHDLbased tools. The Simulation Manager serves as the interface between the design database and commercial VHDL tools. A model groups related design units and other information into a cohesive object, which is used for analysis and simulation. The Simulation Manager uses information in the model to present inputs to the simulator and to store structured simulation results in the database.

3

Figure 2: An Entity Declaration for COUNTER ments. A visual program is a picture specifying a computation. A visual program is not an arbitrary picture, but rather a diagram constructed according to a set of rules describing the class of valid diagrams. Constructs from VHDL are mapped into graphical constructs in vVHDL, and the syntax of vVHDL determines how those constructs can be combined. vVHDL improves textual VHDL in several ways. First, the graphical nature of vVHDL clearly shows the concurrent nature of a design. vVHDL also provides abstraction mechanisms that allow a design to be hierarchically decomposed into a collection of diagrams. The ability to decompose a complex diagram into pieces greatly improves the manageability of a large design. Figure 2 shows an example of an entity declaration for the design entity COUNTER. The interface is constructed by attaching connectors to the outside of a figure. Object declarations attached to the connectors specify the type of interface elements, which in COUNTER are signals. The interface of COUNTER consists of three signals: clear and clock are of mode in, and a is of mode out. Also, clear is initialized to 1. Figure 3 shows an example package declaration for the HiscFunctionsPackage package. The procedure READ has three parameters of types D, T and Natural. The OrResolution function in the lower right has a single input of type TriState-Vector and returns a value of type TriState. In the lower left corner of the package declaration is an include box, which contains some textual VHDL code. This mechanism is used to include code for language aspects not supported directly by the graphical syntax. Lastly, the italicized text is a comment. Figure 4 shows an example of an architecture body

vVHDL

In ViDEO , designs are constructed in vVHDL, a visual programming language based on the VHDL hardware description language. Visual programming languages form programs by combining graphical symbols such as lines, circles, rectangles, and text frag-

365

P

Figure 3: A Package Declaration

Figure 5: Concurrent Signal Assignments

for an entity named SYSTEM, and this architecture body contains six concurrent statements. The buttonlike box in the upper left of Figure 4 is a l i n k box, which is an abstraction mechanism. Elements of a picture can be extracted and placed in their own picture which is then represented by a link box in the original picture. Clicking on the link box will cause the vVHDL editor to open a view of the referenced subpicture. The concurrent statements are drawn using the same basic shape, and an icon (currently one of the letters C, P, B, A, R) distinguishes the type of the concurrent statement. Connectors around the body represent the interface to the concurrent statement. This explicit representation of the interface to all concurrent statements is one of the main advantages

of vVHDL, as it allows dataflow, behavioral and structural models to be mixed within a uniform graphical framework. The bodies of the concurrent statements can be either included directly in the architecture body or specified in a separate subpicture. These statements act as another type of “link box”. Figure 5 is of an architecture body containing two concurrent signal assignments. The labelled connectors on the assignments explicitly represent the interface to the assignment statements in a manner consistent with the other concurrent statements, although this representation is optional. The evaluation of the VHDL expressions contained within the two include boxes in this figure provide the resultant values of the assignment statements.

4

Compiling Visual Designs

The vVHDL compiler processes vVHDL programs, builds an abstract intermediate representation, and translates the visual program into an equivalent textual VHDL program. The vVHDL compiler functions similarly to a traditional compiler, as shown in Figure 6. An input picture is first parsed to recover its syntactic structure. An evaluation phase walks the

Figure 6: Organization of the vVKDL Compiler.

Figure 4: An Architecture for Entity SYSTEM 366

high-level models. This approach combines the natural style of graphical interaction found in schematic capture systems with the advantages of building highlevel behavioral models found in hardware description languages. vVHDL has been used in the design of the Data Collection Chip for the SSC data aquisition system. Our experience indicates that the visual approach to design offers improved understanding, communication and development of designs. The ViDEO environment also demonstrates that an object-oriented database is well suited as a basis for integrating CAD tools. The database provides a flexible, documented interface to persistent data, which simplifies the coding of design tools and the addition of new tools to the environment. Our approach uses an integrated schema to allow the additional information associated with the tools to be attached in a structured manner. Work is continuing on ViDEO in several areas. First, we plan to extend the scope of visual interactions provided by the environment, and support mapping errors uncovered by analysis and simulation back into the visual representation. We also plan to continue to improve the graphical syntax of vVHDL, with an immediate focus on revising the representation of sequential code inside process bodies.

parse tree and constructs an object-oriented intermediate form for representing VHDL designs. A textual VHDL program can be easily generated directly from the intermediate form. The VHDL program essentially plays the role of an executable object file, and is not intended to be viewed by the user. The vVHDL compiler was constructed using the SPARGEN system [7],a compiler generator for visual programming languages. The (two-dimensional) syntax of vVHDL is specified using a grammar, from which a parser is generated. The input to the parser consists of an arbitrarily ordered list of the graphical primitives from an input picture. Each input symbol has attributes specifying the relevant graphical information for the symbol. Action routines associated with productions drive the evaluation phase and build the intermediate form for compiled designs. The intermediate representation for vVHDL programs may be thought of as an abstract syntax for VHDL designs, and could equally well be used as an intermediate form for textual VHDL programs. It is derived from the grammar defining VHDL. [8] Conceptually, a class in this compilation subschema exists for every syntactic construct in the language.

5

Simulating Visual Designs

References

The ViDEO Simulation Manager currently supports analysis and simulation of visual models by the Vantage Spreadsheet tools. The ViDEO data model distinguishes tool-dependent information so that the Simulation Manager can be extended to other VHDL simulators. The simulation of a visual design begins with the creation of a model object, which includes a collection of the design units used and the libraries referenced. Next, model analysis consists of recompilation of some of the units in an order. The units to be recompiled and the order of analysis are dictated by the changes made since analysis and the dependencies between units. A simulation object contains values for generic parameters, inputs to the model, tool-specific options and a collection of signals to monitor. Textual results are extracted from results created by the simulation tool and used to create structured results in the design database. The Simulation Manager creates a persistent record of all inputs to the commercial toolset, which documents the testing of a visual design.

6

[l] C. A. Kuszynski, T. Busfield, A. M. Koelmans, M. R. McLauchlan, and D. J. Kinniment, “Graphical Representation of a Hardware Description Language,” IEEE Proc. on Computers and Digital Techniques, vol. 137, pp. 462467, November 1990. [2] D. Drusinsky and D. Harel, “Using Statecharts for Hardware Description and Synthesis,” IEEE Trans. on Computer-Aided Design, vol. 8, pp. 798-807, July 1989. [3] N. D. Dutt and D. D. Gajski, “Designer Controlled Behavioral Synthesis,” in Proc. of 86th ACM/IEEE Design Automation Conf., pp. 754-757, 1989. [4] J. DeGroat, K. Berk, D. Pompilio, and S. Matechik, ”The AFIT VHDL Environment,” in 1988 Frontiers in Education Conf. Proc., pp. 324-329, 1988. [5] T. Dettmer, A. Rasche, and M. Sohlenkamp, “Concepts for graphical editing of VHDL with AVE,” in Proc. of EURO-VHDL 91,(Stockholm), pp. 184-187, Swedish Inst. of Microelectronics, Sept. 1991. [6] Comdisco Systems, Inc., 919 Hillsdale Blvd., Foster City, CA 94404, Signal Processing Worksystem. [7] E. J. Golin and T. Magliery, “A compiler generator for visual languages,” in 1993 IEEE Conf. on Visual Languages, 1993. (to appear). [8] VHDL Language Reference Manual (IEEE Standard 1076-1987). New York, March 1988.

Conclusions and future work

ViDEO offers a new approach to the design of electronic systems, based on visual representations of

367