Computer Architecture

Dynamic visual attention model in image sequences

Computer Architecture / Visual attention / Segmentation / Feature Extraction / Motion / Motion Segmentation / Object segmentation / Moving Object Recognition / Image Sequence / Feature Integration / Electrical And Electronic Engineering / Motion Segmentation / Object segmentation / Moving Object Recognition / Image Sequence / Feature Integration / Electrical And Electronic Engineering

Arrowhead compliant virtual market of energy

Computer Architecture / Service Oriented Architecture / Job shop scheduling

Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter

Computer Architecture / Power Consumption / Low Power / Spread Spectrum Communication / Surface Area / Feedback loop / Application Specific Integrated Circuit (ASIC) / Feedback loop / Application Specific Integrated Circuit (ASIC)

Real measures, virtual instruments

Computer Architecture / User interfaces / Web Server / Internet

Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture

Computer Architecture / Parallel Programming / Parallel Processing / Synthetic Aperture Radar / High resolution satelite image / Radar Imaging

Using graph patterns to extract scenarios

Computer Science / Computer Architecture / Data Mining / Graph Theory / Documentation / Software Development / Software Architecture / Reverse Engineering / Program Comprehension / Pattern Matching / Source Code / Software Systems / Software System / Software Development / Software Architecture / Reverse Engineering / Program Comprehension / Pattern Matching / Source Code / Software Systems / Software System

MPEG-2 video decompression on a multiprocessing VLIW microprocessor

Computer Architecture / Data Compression / Video Compression / CPU / Instruction Set Architecture / VLIW / Decoding / Instruction Sets / VLIW / Decoding / Instruction Sets

A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture

Computer Architecture / Image Processing / Digital Circuits / Sensor Arrays / Processor Architecture / Cellular Neural Networks / Chip / Cmos Image Sensor / Cellular Neural Network / Electrical And Electronic Engineering / Binary Images / Pixel / Cellular Neural Networks / Chip / Cmos Image Sensor / Cellular Neural Network / Electrical And Electronic Engineering / Binary Images / Pixel

Development environments: A multilevel enactment scenario

Computer Architecture / Software Engineering / Software Development / Programming / Automation / Environment and Development / Process Model / Environment and Development / Process Model

Guest Editors\' Introduction: Multicore SoC Validation with Transaction-Level Models

Computer Architecture / Computer Hardware / Multicore Processing / Electrical And Electronic Engineering

A chip set for lossless image compression

Computer Architecture / Data Compression / VLSI / Image compression / PACS / Frequency / Communication Channels / Pipelines / High Speed / Chip / Image Decomposition / Lossless Image Compression / Digital Image / Lempel Ziv / Electrical And Electronic Engineering / Pixel / Entropy Coding / Lossless Compression / Application Specific Integrated Circuit (ASIC) / Frequency / Communication Channels / Pipelines / High Speed / Chip / Image Decomposition / Lossless Image Compression / Digital Image / Lempel Ziv / Electrical And Electronic Engineering / Pixel / Entropy Coding / Lossless Compression / Application Specific Integrated Circuit (ASIC)

Adaptive track fusion in a multisensor environment

Aerospace Engineering / Computer Architecture / Logic / Numerical Analysis / Adaptive Signal Processing / Kalman Filter / Numerical Simulation / Information Fusion / Sensor Fusion / Accuracy / Distance metric / Bandwidth / Kalman Filter / Numerical Simulation / Information Fusion / Sensor Fusion / Accuracy / Distance metric / Bandwidth

A capstone computer engineering design course

Engineering / Computer Architecture / Education / Computer Science Education / FPGA / Engineering Design / Hardware Description Languages / Field-Programmable Gate Arrays / Vhdl / Arithmetic / Registers / Adders / Engineering Design / Hardware Description Languages / Field-Programmable Gate Arrays / Vhdl / Arithmetic / Registers / Adders

Fractal Image Compression on Spiral Architecture

Computer Architecture / Computer Vision / Image Processing / Computational Geometry / Pattern Recognition / Fractals / Image / Processing Speed / Image compression / Image Reconstruction / Edge Detection / Fixed Point Theory / Object Recognition / Storage / Iterated Function System / Complete Metric Space / Spirals / Pixel / Application Software / Compression Ratio / Fractal Image Compression / Fractals / Image / Processing Speed / Image compression / Image Reconstruction / Edge Detection / Fixed Point Theory / Object Recognition / Storage / Iterated Function System / Complete Metric Space / Spirals / Pixel / Application Software / Compression Ratio / Fractal Image Compression

Semiótica de la acción: textualización y notación

Semiotics / Computer Architecture / Visual Communication / Theories of Social Practices

Triton/1: A Massively-Parallel Mixed-Mode Computer Designed to Support High Level Languages

Computer Architecture / Informatics / Parallel Programming / Parallel Processing / Hardware / Computer Languages / Mixed Mode / Integrated design / Parallel Computer / Software Performance / Computer Languages / Mixed Mode / Integrated design / Parallel Computer / Software Performance

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